Active solid-state devices (e.g. – transistors – solid-state diode – Encapsulated
Reexamination Certificate
1999-07-09
2001-05-01
Mis, David (Department: 2817)
Active solid-state devices (e.g., transistors, solid-state diode
Encapsulated
C257S734000, C257S735000, C257S738000, C257S783000
Reexamination Certificate
active
06225703
ABSTRACT:
FIELD OF THE INVENTION
The present invention pertains to a type of semiconductor device having a package structure preferred for reducing warping of the package.
BACKGROUND OF THE INVENTION
Usually, in order to protect the semiconductor chip from moisture and ambient pollution the semiconductor devices is sealed with a plastic, ceramic, or a molding resin. In consideration of mass productibility, cost, and other factors, the packaging using the transfer mold forming method is most widely adopted at the present time. In the transfer mold forming method, the semiconductor chip assembly is placed in the mold die, and a thermosetting resin is flowed into the die. The die is brought to a high temperature to cure the resin, forming a package with the chip sealed therein.
There are several intrinsic problems with the transfer mold forming method that must be taken into consideration when the method is used. One problem is related to the warping of the molded semiconductor package. In the case of mold forming, curing is carried out at a temperature as high as 175° C., and the package is then cooled naturally to room temperature. In this case, warping occurs due to the difference between the linear expansion coefficient of silicon as the raw material of the semiconductor chip and the phenol based, epoxy-based or other thermosetting resin used as the molding resin. The warping leads to uneven contact of the connecting terminals on the substrate when the semiconductor package is assembled on a printed-circuit board. As a result, the assembly reliability deteriorates. Also, the larger the package or the chip, the greater the adverse influence of the warping of the package relative to its flatness. As a result, it becomes difficult to effect a highly reliable assembly process.
A method used to solve this problem is forming the molding resin on both sides of the semiconductor chip to the same thickness, that is, centering the semiconductor chip with respect to the package. However, this method cannot be used for certain types of packages. One of these packages is the BGA (Ball Grid Array) package. In the BGA package, the semiconductor chip is attached to an insulating substrate that has solder bumps in a two-dimensional arrangement, and the semiconductor chip is covered. On the insulating substrate, that is, on the surface on the side opposite to the solder bump forming surface of the insulating substrate, the molding resin is used to form the outer shape of the semiconductor device. In this case, the difference between the linear expansion coefficient of the molding resin and the insulating substrate leads to warping. Another semiconductor device that has a structure that does not allow the semiconductor chip to be centered relative to the package is the TQFP (Thin Quad Flat Package), which has an exposed die pad for heat dissipation purposes.
In order to minimize the warping of the package of this type of semiconductor device, it is effective to reduce the thickness of the molding resin. However, since the conductor wires are lead out from the principal surface of the semiconductor chip, the resin should at least be of sufficient thickness to entirely cover and shield the wires.
Consequently, the purpose of the present invention is to minimize the warping of the package caused by thermal contraction in the aforementioned semiconductor device.
SUMMARY OF THE INVENTION
The semiconductor device of the present invention comprises a semiconductor chip with first and second surfaces, and plural electrode pads on one surface. The semiconductor chip supported on a substrate comprising an insulating substrate and die pads, etc., with its first surface facing the substrate. The semiconductor device also contains conductor leads for electrically connecting the aforementioned semiconductor chip to the outside. The conductor leads and the electrode pads of the semiconductor chip are electrically connected to each other through a connecting means comprising conductor wires and conductor bumps, etc. With a portion of the aforementioned conductor leads exposed, the aforementioned semiconductor chip, the aforementioned conductor leads, and the aforementioned connecting means are sealed by the molding resin. The molding resin determines, the outer shape of the semiconductor device. According to the present invention, the semiconductor device has a plate-shaped member which is positioned on the second surface of the aforementioned semiconductor chip and is sealed by the aforementioned molding resin together with the aforementioned semiconductor chip. The plate-shaped member has a linear expansion coefficient that is less than the linear expansion coefficient of the aforementioned molding resin. By using a plate-shaped member with a relatively low linear expansion coefficient and placing on the semiconductor chip, it is possible to suppress the thermal contraction on the upper side of the semiconductor chip. Also, the presence of the plate-shaped member on the semiconductor chip substantially reduces the thickness of the molding resin on the semiconductor chip. The pulling force caused by the contraction of the molding resin generated by the warping is proportional to its thickness. Consequently, with the semiconductor device of the present invention that contains the aforementioned plate-shaped member, it is possible to suppress the warping of the package to a very low level.
According to the present invention, the linear expansion coefficient of the aforementioned plate-shaped member is preferably in the range of 1-20 ppm, and its modulus of elasticity is preferably in the range of 800-15,000 kg/mm
2
. Examples of materials that have these properties include polyimide resin, ceramics, silicon, etc.
Also, it is preferred that the aforementioned plate-shaped member be bonded to the second surface of the aforementioned semiconductor chip.
Also, it is preferred that the aforementioned electrode pads be formed on the periphery of the second surface of the aforementioned semiconductor chip, and that the aforementioned plate-shaped member be located within the region surrounded by the electrode pads.
Also, the thickness of the aforementioned molding resin on the surface of the aforementioned plate-shaped member is preferably in the range of 0.05-0.4 mm. The thickness of the aforementioned plate-shaped member is preferably in the range of 0.08-1.0 mm.
An embodiment of the present invention will be explained below.
FIGS. 1 and 2
illustrate an example of application of the present invention in BGA type semiconductor device
9
. BGA type semiconductor device
9
has flexible insulating substrate
2
which is planar and is larger by a predetermined amount than semiconductor chip
1
it supports. In the application example, flexible insulating substrate
2
is a straight-chain nonthermoplastic polyimide with a thickness of about 70 &mgr;m (trade name: Eupirex [transliteration]). The upper surface of flexible insulating substrate
2
contains conductor pattern
3
formed by etching a copper foil. One end of each of the wires of conductor pattern
3
is connected through a via hole on the substrate to one of solder bumps
4
arranged in a two-dimensional configuration on the surface of the opposite side. The other end of each wire extends to the periphery of flexible insulating substrate
2
, and is arranged such that one end of conductor wire
5
can be bonded.
Semiconductor chip
1
is bonded to flexible insulating substrate
2
with die-bonding material
6
. Most of conductor pattern
3
formed on flexible insulating substrate
2
is covered with semiconductor chip
1
, only the end portion extending in the periphery of the substrate is exposed on the upper surface of the peripheral portion of flexible insulating substrate
2
. In the peripheral portion of the principal surface of semiconductor chip
1
, that is, the surface where the circuit elements are formed, electrode pads
1
a
are arranged side by side in a columnal configuration. Conductor wire
5
extends from each electrode pad
1
a
and is bond
Azuma Chikara
Karashima Akira
Umehara Norito
Kempler William B.
Mis David
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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