Static information storage and retrieval – Powering
Reexamination Certificate
2000-10-30
2001-09-04
Nelms, David (Department: 2818)
Static information storage and retrieval
Powering
C365S189110, C365S189090, C365S189070, C327S536000, C327S537000
Reexamination Certificate
active
06285622
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and, in particular, to a semiconductor device having a circuit which generates an internal potential by a charge pump.
2. Description of the Background Art
Recently, semiconductor devices in which a large number of transistors are integrated are used in various electrical equipment, such as workstations and personal computers. Of these semiconductor devices, a DRAM is used as a main memory of personal computers. This DRAM has a charge pump for stetting up power-supply potential.
FIG. 11
is a block diagram of a boost circuit contained in a conventional DRAM.
Referring to
FIG. 11
, the DRAM has a boost circuit
1
normally operating, and a boost circuit
2
that operates when the DRAM is active. Step-up potential V
PP
is outputted by the boost circuits
1
and
2
. The boost circuit
1
includes a detecting circuit
3
that compares and amplifies reference potential V
REF
and input potential V
IN
. The input potential V
IN
obeys the step-up potential V
PP
. The boost circuit
1
further includes a buffering circuit for buffering the output of the detecting circuit
3
, a clock generating circuit
5
that outputs a clock signal in response to the output of the buffering circuit
4
, and a charge pump
6
driven by the output of the clock generating circuit
5
. The charge pump
6
has a low capability of supplying step-up potential V
PP
, but has a low power consumption.
The boost circuit
2
comprises a detecting circuit
7
that compares and amplifies reference potential V
REF
and input potential V
IN
, a buffering circuit
8
for buffering the output of the detecting circuit
7
, and an AND gate
9
that receives the output of the buffering circuit
8
and signal ACTL indicating the activation of the DRAM. The signal ACTL reaches its high level when the DRAM is active. The boost circuit
2
further comprises a clock generating circuit
10
that outputs a clock signal in response to the output of the AND gate
9
, and a charge pump
11
driven by the output of the clock generating circuit
10
. The charge pump
11
has a higher capability of supplying step-up potential V
PP
than the charge pump
6
.
When the signal ACTL is at its low level indicating the inactive state, from the output of the AND gate
9
, a low level is outputted regardless of the detection result of the detecting circuit
7
. In response to this low level output, the clock generating circuit
10
stops oscillation of a clock signal. Then, the boost circuit
2
stops step-up operation, and only the boost circuit
1
executes step-up operation.
It is designed so that the detecting circuits
3
and
7
have the same detecting level. However, because of change in process, the detecting circuit
7
can be ahead of the detecting circuit
3
in detecting a decrease in step-up potential V
PP
. Such a circuit has caused the following problems. That is, when signal ACTL is at its low level indicating the inactive state, the detecting circuit
7
detects a decrease in step-up potential V
PP
whereas the detecting circuit
3
does not detect it in some cases. In this case, both clock generating circuits
5
and
10
stop a clock signal oscillation, and both boost circuits
1
and
2
stop step-up operation. As a result, the output node of the detecting circuit
7
becomes an intermediate potential, and a through current passing through the subsequent buffering circuit
8
.
SUMMARY OF THE INVENTION
According to a first aspect of the invention, a semiconductor device comprises: a first internal potential generating circuit including: a first detector for detecting a deviation from a predetermined level of an internal potential, a buffer circuit for receiving the output of the first detector, a control circuit for supplying a clock enable signal which becomes disable regardless of the output of the buffer circuit when an activation signal indicates the inactive state, and which is responsive to the output of the buffer circuit when the activation signal indicates the active state, a first oscillator that oscillates a first clock signal in response to the clock enable signal, and a first charge pump that generates the internal potential at an output node, according to the first clock signal; and a second internal potential for generating circuit including: a second detector that is ahead of the first detector in detecting a deviation from the predetermined level of the internal potential, a second oscillator that oscillates a second clock signal in response to the output of the second detector, and a second charge pump that generates the internal potential at the output node, according to the second clock signal.
According to a second aspect, the semiconductor device of the first aspect is characterized in that the second charge pump has a smaller capability of supplying the internal potential than the first charge pump.
According to a third aspect, the semiconductor device of the first aspect is characterized in that the second internal potential generating circuit further includes a buffer circuit for receiving the output of the second detector and supplying a clock enable signal to the second oscillator.
According to a fourth aspect, the semiconductor device of the first aspect is characterized in that the second detector detects a deviation from the predetermined level of the internal potential, based on the result of a comparison of a reference potential with an internal potential related potential related to the internal potential.
According to a fifth aspect, the semiconductor device of the fourth aspect further comprises: a level shifter for performing level shifting of the internal potential to supply a shift potential, the internal potential related potential includes the shift potential, characterized in that the second detector includes a current mirror circuit, and first and second transistors which are connected to the current mirror circuit and receive at their respective gates the shift potential and the reference potential, the first and second transistors have different current drive capabilities.
According to a sixth aspect, the semiconductor device of the fifth aspect is characterized in that the first and second transistors are of a first conductivity type, the current mirror circuit includes a third transistor of a second conductivity type having a drain and gate connected to the drain of the first transistor in common, and a fourth transistor of the second conductivity type having a drain connected to the drain of the second transistor, and having a gate connected to the gate of the third transistor; the second transistor has a greater channel width than the first transistor; and the output of the second detector is supplied from between the drains of the second and fourth transistors.
According to a seventh aspect, the semiconductor device of the first aspect is characterized in that the first detector detects a deviation from the predetermined level of the internal potential, based on the result of a comparison of a reference potential with an internal potential related potential related to the internal potential; and the second detector detects a deviation from the predetermined level of the internal potential, based on the result of a comparison of the reference potential with the internal potential related potential.
According to an eighth aspect, the semiconductor device of the seventh aspect further comprises: a level shifter for performing level shifting of the internal potential to supply a shift potential, the internal potential related potential including the shift potential, characterized in that the first detector includes a first current mirror circuit, and first and second transistors which are connected to the first current mirror circuit and receive at their respective gates the shift potential and the reference potential; the second detector includes a second current mirror circuit, and third and fourth transistors which are connected to the second current minor circu
Haraguchi Masaru
Nakaoka Yoshito
Yamasaki Kyoji
Lam David
Mitsubishi Denki & Kabushiki Kaisha
Nelms David
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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