Semiconductor device

Details Semiconductor device Semiconductor device

2000-01-07

2001-07-24

Wojciechowicz, Edward (Department: 2815)

Valves and valve actuation

Limit stop

Rotary valve

C257S328000, C257S401000, C257S408000

Reexamination Certificate

active

06264167

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor device having a double diffusion MOSFET, more particularly to a semiconductor device which has a lateral type double diffusion MOSFET available for integrated circuit devices wherein each cell has its drain electrode taken out from the top.
BACKGROUND OF THE INVENTION
A double diffusion MOSFET (hereinafter referred to as a DMOS) is applied widely for power IC's or motor drivers because it can withstand high voltage compared to an ordinal MOSFET and because of its comparatively low on-resistance (operating resistance) R
on
.
For this type of MOSFET, one of the important characteristics together with the withstand voltage is the operating resistance, and particularly a lower on-resistance (operating resistance) R
on
has been required for recent electrical apparatuses wherein a low power consumption is desired. In general, to reduce R
on
, not to speak of optimizing the device configuration, the optimization of manufacturing conditions is important. In case those conditions are optimized, however, by changing the gate width of the DMOS, the operating resistance R
on
is adjusted. That is to say, by broadening the gate width, R
on
can be made smaller, and if the gate width becomes twice as wide, then R
on
becomes a half, and if the gate width is tripled, then the R
on
becomes one third. When the gate width is widened, however, the chip area becomes larger in general and the cost for that is increased. Therefore, it has become a problem to be solved to broaden the gate width without increasing the chip area.
Gate patterns for each cell of conventional DMOSFET are shown in FIGS.
3
(
a
) to
3
(
e
). And in each of the FIGS., an S stands for a source contact part and a D stands for a drain contact part, respectively.
In FIG.
3
(
a
), an orthodox design called a stripe type gate is shown, of which gate width is not wide enough per unit area. Because of the simple design, however, it is easy for a layout and widely used.
The structure shown in FIG.
3
(
b
) is a design called a mesh type gate, and if it is processed with the same vertical structure and the process precision as the stripe type structure in FIG.
3
(
a
), it is possible for the gate width per unit area to be 1.15 times as large as that of the stripe type structure. This mesh type structure is widely known and is actually utilized. However, because of the corner part C which bends 90 degrees, the withstand voltage is somewhat lowered and side wall spacers formed on the poly-silicon wall of the gate or the like are different in the linear parts and in the corner parts, which serves as demerits.
The structure shown in FIG.
3
(
c
) is a honeycomb type gate, and the gate width per unit area is 1.18 times as large as that of the stripe type, but this is originally designed to be used for the vertical type DMOS structure (the whole parts of this pattern are used as a source and a drain is taken out from the backside of the substrate in this structure), therefore, if they are used as sources S and drains D for alternate lines as shown in the Figure, a non working area shown as A in FIG.
3
(
c
) exists (the source and the drain are too far away and the area in between can not be utilized as a channel), the effective gate width becomes 0.82 times as large as that of the stripe type, which does not have any merits in the lateral type DMOS.
The structure shown in FIG.
3
(
d
) has a form where the mesh type and the honeycomb type are combined. In this structure, the gate width per unit area is 1.1 times as large as that of the stripe type, the distance between the source contact to the gate is locally long (See B), which is a demerit for allowing a parasitic npn transistor to operate easily.
FIG.
3
(
e
) shows a circular gate, of which gate width per unit area is 1.6 times as large as that of the stripe type and since it does not have a corner part, the structure does not have a difficulty with controlling the withstand voltage or the vertical structure while being under construction.
However, since it has a non working area A and there is a part where the drain area is pinched (the portion of E), it can not be said to be the best form.
As described above, each of the conventional gate structures has merits and demerits, and accompanying the miniaturization of electric apparatuses for the portability, it is required to further reduce the power consumption and is required to have a DMOS of a wider gate width in the same chip area.
SUMMARY OF THE INVENTION
In review of the above mentioned situation, it is a purpose of the present invention to provide a semiconductor device having a lateral type DMOS which can increase the gate width per unit area and can increase withstand voltage.
A semiconductor device according o the present invention has a lateral type double diffusion MOSFET comprising: a semiconductor layer of a first conductivity type as a drain region; a plurality of body regions comprising a plurality of diffusion regions of a second conductivity type formed regularly on a surface of the semiconductor layer; source regions of the first conductivity type, each of which being formed within each of the plurality of body regions with a certain interval from the periphery; gate electrodes formed through an insulator film on the surface of channel regions between the source regions and the drain region; and drain cells, each of which being surrounded by some of the plurality of body regions and is provided with a contact region for an electrode, wherein the body regions being formed as an octagon on a plane, and the drain cells being formed as a quadrilateral on the plane.
More concretely, it has a structure where, the octagon of the body regions have long sides and short sides connected alternately on the plane, the short sides being formed by cutting off the corners of a quadrilateral, and the body regions and the drain cells are formed so that the drain cells are provided in contact with one of the long sides and one of short sides of adjoining body regions is in contact with one of the short sides.
By having this structure, corners of the body regions, which have the difficulty in functioning effectively as part of the channel width, are shaved so that the corners are rounded and adjoining body regions border on those parts, thereby, the number of cells (body regions and drain cells) has been increased to make larger the gate width of per unit area. As a result, a semiconductor device can be gained which has a lateral double diffusion MOSFET with a smaller operating resistance.
As the long sides are formed to have equal lengths and the short sides are formed to have equal lengths, respectively, and the body regions and the drain cells are arranged alternately to be in a matrix, they can be more effectively arranged.
By having the semiconductor layer of the first conductivity type working as the drain region which is a semiconductor layer formed by epitaxial growth on a semiconductor substrate of the second conductivity type, it becomes easier to form an IC integrated with other circuit elements, and by having a buried layer of a high density purity of the first conductivity type which is provided on the interface between the semiconductor substrate under the body regions and the semiconductor layer of the first conductivity type, it has become easy to lower the resistance of the entire device.
And it is preferable for the source regions being provided along the outer periphery of the body regions in a ring form, and a high density impurity region of the second conductivity type being formed in the central part of the ring form. By this structure, the electric potential of the body regions becomes equal to that of the source regions to stabilize the threshold voltage V
th
of DMOS, and to prevent a parasitic npn transistor from operating.


REFERENCES:
patent: 5744826 (1998-04-01), Takeuchi et al.

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