Semiconductor device

Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude

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Details

327103, 327227, 3652335, H03K 5153, H03K 3033, G01R 2902

Patent

active

056191510

ABSTRACT:
A semiconductor memory device which includes at least one of (1) an input buffer circuit which generates internal address signals in response to an incoming address; (2) a decoder circuit formed of plural logic gates each of which is composed of the combination of MOS and bipolar circuitry; (3) a sense amplifier circuit including a multiemitter transistor; (4) a signal or address transition detector circuit which includes input circuits each receiving, for example, an address signal of a voltage amplitude and outputting a current amplitude signal in response to a change in level of the address signal, and a detector circuit connected thereto which has a cascode amplifier arranged such that it receives current amplitude signals at an input thereof and in which the cascode amplifier input is maintained at a substantially constant voltage, in which the detection circuit detects a transition of one or more of the current amplitude signals and, in response thereto, generates an ATD signal of a voltage amplitude; and (5) an output buffer circuit, in which the decoder, sense amplifier and output buffer of the device are controlled in accordance with signals from a clock generator, which is responsive to the ATD signal.

REFERENCES:
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patent: 4797583 (1989-01-01), Ueno et al.
patent: 4893282 (1990-01-01), Wada et al.
patent: 4916668 (1990-04-01), Matsui
patent: 4962478 (1990-10-01), Matsuda
patent: 4982117 (1991-01-01), Matsuzaki et al.
patent: 5008858 (1991-04-01), Ikeda
patent: 5018107 (1991-05-01), Yoshida
patent: 5200926 (1993-04-01), Iwahashi et al.
Electronic Product Design, Oct. 1980, "Generating Narrow Pulses with C.M.O.S. Logic", Macleod, et al., p. 21.

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