Semiconductor device

Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix

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Details

345204, 349149, G09G 336

Patent

active

060087889

DESCRIPTION:

BRIEF SUMMARY
FIELD OF THE INVENTION

This invention relates to a semiconductor device and, in particular, to a semiconductor device for controlling and driving display devices.


DESCRIPTION OF THE RELATED ART

Nowadays, liquid crystal display panels (hereinafter referred to as "LCD panels") are being used in the display sections of OA apparatus, such as facsimile apparatus and copying machines, and AV apparatus, such as audio apparatuses and VTR, and various types of LSI for controlling and driving such LCD panels have been developed.
FIG. 9 is a plan view showing a conventional microcomputer having a built-in controller and drivers for controlling and driving a LCD panel. In the drawing, numeral 1 indicates a CPU for data operation and for controlling the entire system; numeral 2 indicates a ROM for storing commands from the CPU 1; numeral 3 indicates a RAM for storing data for the operations conducted by the CPU 1; numeral 4 indicates a timing signal generation circuit for generating signals for effecting timing control of various operations on the basis of clock signals; numeral 5 indicates a LCD controller for controlling a LCD panel 15 (see FIG. 10); numeral 6 indicates a common driver for outputting signals for driving scanning electrodes (COM 0 through 15) of the LCD panel 15 upon receiving signals from the LCD controller 5; numeral 7 indicates a LCD display RAM for supplying display data set by the CPU 1 to a segment driver 8; numeral 8 indicates the segment driver for outputting signals for driving signal electrodes (SEG 0 through 79) (see FIG. 10) of the LCD panel 15 upon receiving the output of the LCD display RAM 7; and numeral 9 indicates a semiconductor chip realized by forming these components, indicated by numerals 1 through 8, on the same semiconductor substrate. Numeral 10 indicates common terminals COM 0 through 15 which are opposed to a side of the semiconductor chip 9 and arranged continuously along this side at intervals, for example, of 0.50 mm and which are used to extract the signals output from the common driver 6; numeral 11 indicates segment terminals SEG 0 through 79 which are opposed to sides of the semiconductor chip 9 and arranged continuously along these sides at intervals, for example, of 0.50 mm and which are used to extract the signals output from the segment driver 8; and numeral 12 indicates external terminals which are opposed to sides of the semiconductor chip 9 and continuously arranged along these sides, adjacent to the common terminals 10 and segment terminals 11, at intervals, for example, of 0.50 mm and which are used to input and output signals which are other than those output from the common driver 6 and the segment driver 8 and which are necessary for the operation of the semiconductor chip 9. Numeral 13 indicates a flat package (semiconductor device) sealing the semiconductor chip 9 in such a way that the terminals 10 to 12 are exposed on the outside.
FIG. 10 is a plan view showing a multi-layer printed circuit board packaging a LCD panel having scanning electrodes (COM 0 through 15) on a pair of opposed sides thereof and a conventional microcomputer as shown in FIG. 9. In the drawing, numeral 14 indicates the multi-layer printed circuit board; numeral 15 indicates a LCD panel mounted on the multi-layer printed circuit board 14; numeral 17 indicates signal electrodes (SEG 0 through 79) of the LCD panel 15 which receive signals from the segment driver 8; numeral 16 indicates scanning electrodes (COM 0 through 15) of the LCD panel 15 which receive signals from the common driver 6; numeral 18 indicates a printed wiring group on the first layer of the multi-layer printed circuit board 14 and connecting COM 0 through COM 7 of the common terminals 10 to COM 0 through COM 7 of the scanning electrodes 16; and numeral 19 indicates a printed wiring group on the first and second layers of the multi-layer printed circuit board 14 and connecting COM 8 through COM 15 of the common terminals 10 to COM 8 through COM 15 of the scanning electrodes 16. In the drawing, the broken lines in

REFERENCES:
patent: 4613855 (1986-09-01), Person et al.
patent: 4684974 (1987-08-01), Matsunaga et al.
patent: 4985663 (1991-01-01), Nakatani
patent: 5260698 (1993-11-01), Munetsugu et al.

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