1987-06-03
1989-04-04
Edlow, Martin H.
357 67, 357 49, 357 237, 357 234, H01L 2712
Patent
active
048190373
ABSTRACT:
In a semiconductor device having mainly vertical semiconductor elements, a plurality of semiconductor elements are formed in spaced relationship from each other on an insulation layer formed on a substrate and therefore completed isolated electrically from each other. A plurality of semiconductor intermetallic compound layers used as electrodes are formed independently in the same spaced relationship as the semiconductor elements for the respective semiconductor elements, making it possible to determine the potential for each semiconductor element as desired. Both N-type DMOS and P-type DMOS or the like can thus be formed on a single seminconductor single crystal substrate.
REFERENCES:
patent: 4685199 (1987-08-01), Jastrzebski
patent: 4748485 (1988-05-01), Vasudev
IEE Transactions on Electron Devices, vol. Ed-27, No. 2, Feb. 1980, "Modeling of the On-Resistance of LDMOS, VDMOS, and VMOS Power-Transistors", S. C. Sunn and James D. Plummer, pp. 356-367.
Hattori Tadashi
Katada Mitutaka
Ohta Minoru
Sakakibara Nobuyoshi
Tominaga Takayuki
Edlow Martin H.
Nippon Soken Inc.
Prenty Mark
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