Semiconductor device

Details Semiconductor device Semiconductor device

1994-10-13

1996-07-09

Nelms, David C.

Static information storage and retrieval

Interconnection arrangements

Transistors or diodes

365 51, 365 63, 365149, 257296, G11C 506

Patent

active

055351530

ABSTRACT:
A semiconductor device has a plurality of cell arrays each comprising a plurality of memory cells each composed of an MIS transistor and a capacitor formed from a conductive layer, a plurality of word lines and bit lines intersecting each other at the memory cells, a plurality of sense amplifiers alternating with the cell arrays, a plurality of row decoders, a plurality of column decoders, each of the column decoders being connected to and shared by a plurality of the sense amplifiers, and a plurality of interconnections for transmitting selective signals from the word lines, the bit lines and the column decoders. The interconnections for transmitting selective signals from the bit lines and the column decoders extend in the direction in which the cell arrays and the sense amplifiers are arrayed. The interconnections for transmitting selective signals from the word lines, the bit lines and the column decoders are formed from three different layers, other than the conductive layer for forming a capacitor, on the cell arrays. The interconnections for transmitting selective signals from the column decoders are formed from a metallic layer on the cell arrays.

REFERENCES:
patent: 5361233 (1994-11-01), Kotani
T. Sugibayashi et al., "WP 3.5: A 30ns 256Mb DRAM with Multi-Divided Array Structure," IEEE International Solid-State Circuits Conference, Feb. 24, 1993, pp. 50-51.
K. Noda et al., "A Boosted Dual Word-line Decoding Scheme for 256Mb DRAMs," 1992 Symposium on VLSI Circuits Digest of Technical Papers, pp. 112-113.

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