Semiconductor device

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357 2311, 357 234, 357 231, 357 30, 357 45, H01L 2978

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045716072

ABSTRACT:
The capacity of a capacitor constituted by a metal-insulator-semiconductor layer configuration varies depending on the quantity of electric charge staying in the neighborhood of the interface between the insulating layer and the semiconductor layer. Because interleaving of a thin semiconductor layer between the insulating layer and the semiconductor layer to form a P-N junction therebetween is effective to confine some quantity of electric charge in the thin semiconductor layer, the capacity of the capacitor can be regulated. When the quantity of electric charge confined in the thin semiconductor layer is given in the form of an electric pulse signal, the signal can be memorized in the form of capacity. A layer configuration of a conductor, an insulator and a semiconductor, including a P-N junction therein fabricated on a substrate with which the layers are isolated, functions as a memory cell which consists of only one capacitor and, which requires an extremely small area of a chip, and which is involved with non destructive read out. The same layer configuration is effective to function as a photoelectro transducer or an image sensor unit, when the conductor layer is fabricated with a transparent conductor.

REFERENCES:
patent: 3882531 (1975-05-01), Michon
patent: 3893146 (1975-07-01), Heeren
patent: 3979734 (1976-09-01), Pricer et al.
patent: 3988613 (1976-10-01), Brown
patent: 4329704 (1982-05-01), Sakurai
patent: 4373248 (1983-02-01), McElroy
Electronics, vol. 51, No. 26 (1972, pp. 31-32.
Richman, Paul MOS Field-Effect Transistors and Integrated Circuits, Wiley-Interscience, N.Y., pp. 46-53.
Bulk Access-Surface Storage Memory Cells; W. P. Noble, Jr.; IBM Technical Disclosure Bulletin, vol. 16, No. 10, Mar. 1974, pp. 3170-3172.
Simple Cell Design for Dynamic RAM Scraps Capacitor; 8032 Electronics, vol. 51, No. 26 (1978.12), pp. 31-32.
Three-Terminal Charge-Injection Device, Paul G. A. Jespers and Jean Marie Millet, IEEE Journal of Solid-State Circuits, vol. SC-11, No. 1, Feb., 1976, pp. 133-139.

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