Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support
Patent
1998-03-24
1999-01-26
Tsai, Jey
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Metallic housing or support
438126, 438127, 438106, H01L 2144, H01L 2148, H01L 2150
Patent
active
058638172
ABSTRACT:
As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
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Anjo Ichiro
Eguchi Syuuji
Hasebe Akio
Hozoji Hiroshi
Ichitani Masahiro
Hitachi , Ltd.
Tsai Jey
Zarneke David A.
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