1986-10-21
1987-07-14
Edlow, Martin H.
357 13, 357 48, H01L 2956, H01L 2990, H01L 2704
Patent
active
046806008
ABSTRACT:
A semiconductor device such as a TTL-type integrated circuit device which has an input protection circuit for each inner circuit, e.g., each TT logic gate. The input protection circuit is formed on a semiconductor substrate of a first conductivity type, and includes a first impurity region having a second conductivity type connected to an external terminal and an island-shape formed on the semiconductor substrate surrounded by an isolation region having the first conductivity type. The device also includes a clamp diode formed on an electrode layer contacting with the first impurity region. The device further includes a PN junction type protection diode formed on a second impurity region having the first conductivity type; the protection diode crosses the first impurity region between the clamp diode and a portion of the first impurity region connected to the external terminal and reaches the isolation region. The reverse withstand voltage of the PN junction type protection diode is smaller than that of the clamp diode, thereby preventing excessive reverse current flow and avoiding permanent destruction of the clamp diode.
REFERENCES:
patent: 4110775 (1978-08-01), Festa
patent: 4276556 (1981-06-01), Enomoto et al.
"The Bipolar Digital Integrated Circuits Data Book for Design Engineers", Part 1, 1981, Japan, Texas Instruments Incorporated, p. 6-3 & p. 6-9.
Enomoto Hiromu
Tahara Akinori
Yasuda Yasushi
Edlow Martin H.
Fujitsu Limited
Lamont John
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