1989-01-13
1991-02-05
James, Andrew J.
357 43, 357 38, H01L 2978
Patent
active
049909789
ABSTRACT:
A semiconductor substrate is provided thereon with an insulated gate bipolar transistor which is a composite element of a pnpn thyristor and an N-channel MOS-FET. In order to monitor operating current of the insulated gate bipolar transistor, a monitor terminal is provided in addition to collector, emitter and gate terminals. The operating current of the insulated gate bipolar transistor is monitored through the monitor terminal to perform appropriate protective operation when the operating current reaches a critical region, thereby to prevent occurrence of a latch-up phenomenon.
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patent: 4672407 (1987-06-01), Nakagawa
patent: 4672584 (1987-06-01), Tsuji
patent: 4760431 (1988-07-01), Nakagawa
IBM Technical Disclosure Bulletin, vol. 22 #12, pp. 5291-5293 by Garnache, May 1980.
"An Analytical Model for the Power Bipolar-MOS Transistor", Solid State Electronics, vol. 29, No. 12, 1986, pp. 1229-1237.
"Optimization of Epitaxial Layers for Power Bipolar-MOS Transistor", IEEE Electron Device Letters, vol. ELD-7, No. 9, 1986, pp. 510-512.
"MOSFET Measures Current with No Loss", Electronic Design, Feb. 20, 1986.
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James Andrew J.
Mitsubishi Denki & Kabushiki Kaisha
Prenty Mark
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