Semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads

Reexamination Certificate

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Details

C257S678000, C257S693000, C257S758000, C257S773000, C257S776000

Reexamination Certificate

active

08084859

ABSTRACT:
In a wafer level CSP package, with respect to signal wiring9bdisposed in a signal wiring disposition forbidden region16in the vicinity of external output terminals disposed in a package outer peripheral portion, since a stress generated at signal wiring9can be dispersed by disposing dummy wiring9aaround the signal wiring9bor by expanding the width of the signal wiring itself, occurrences of cracks in a surface protective film can be readily suppressed.

REFERENCES:
patent: 5539551 (1996-07-01), Nomoto et al.
patent: 2002/0140083 (2002-10-01), Matsuda
patent: 07-273292 (1995-10-01), None

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