Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including high voltage or high power devices isolated from...
Reexamination Certificate
2004-08-17
2010-06-22
Gurley, Lynne A (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including high voltage or high power devices isolated from...
C257S501000, C257S493000, C257S481000, C257SE29265, C257SE21421
Reexamination Certificate
active
07741695
ABSTRACT:
Extending from an upper surface of an n−semiconductor layer on a p−semiconductor substrate to the interface between the n−semiconductor layer and the p−semiconductor substrate, a p+impurity region is provided. The p+impurity region defines a high-potential island region, a low-potential island region and a slit region in the n−semiconductor layer. The n−semiconductor layer in the high-potential island region and the n−semiconductor layer in the low-potential island region are connected by the n−semiconductor layer in the slit region, and a logic circuit is formed in the n−semiconductor layer in the high-potential island region. A width in the direction of Y axis of the n−semiconductor layer in the slit region is set to be narrower than a width in the direction of the Y axis of the n−semiconductor layer in the high-potential island region.
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German Office Action Issued in German Application No. 10 2004 059 627.1-33 dated Nov. 30, 2007.
Gebremariam Samuel A
Gurley Lynne A
McDermott Will & Emery LLP
Mitsubishi Denki & Kabushiki Kaisha
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