Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
2008-03-26
2010-12-21
Pert, Evan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257SE23010
Reexamination Certificate
active
07855453
ABSTRACT:
Provided is a semiconductor device in which a high concentration n type impurity region to be a conductive path and a drain electrode are disposed in an outer circumferential end of the chip to be an inactive region as a device region. Thereby, an up-drain structure is obtained without reducing the device region or without increasing the size of a semiconductor chip. The provided n type impurity region and drain electrode causes a depletion layer of a substrate to be terminated without needing an additional conventional annular region or shield metal. This is because the n type impurity region and the drain electrode also function as the annular region and the shield metal, respectively. With this configuration, a MOSFET with the up-drain structure having necessary components is obtained, while avoiding a reduction of the device region or an increase of the chip area.
REFERENCES:
patent: 6563169 (2003-05-01), Miyakoshi et al.
patent: 2006/0030142 (2006-02-01), Grebs et al.
patent: 2008/0237631 (2008-10-01), Watanabe
patent: 2002-353452 (2002-12-01), None
patent: 2005-101334 (2005-04-01), None
Miyata Takuji
Yoshida Tetsuya
Morrison & Foerster / LLP
Pert Evan
Sanyo Electric Co,. Ltd.
Sanyo Semiconductor Co. Ltd.
Soderholm Krista
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