Semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum

Reexamination Certificate

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Details

C257S759000, C257S760000, C257S401000, C257S202000, C257S288000

Reexamination Certificate

active

07812453

ABSTRACT:
The present invention proposes a dummy metal fill structure which makes it possible to reduce variations in transistor characteristics as much as possible even if mask misalignment occurs, as well as to ensure the intended planarizing effect of the metal CMP process. The dummy metal fill formed above the gate electrode extends in the gate length direction with both ends thereof protruding from a region corresponding to the gate electrode. Even if a mask for forming a wiring layer is misaligned and the position of the dummy metal fill is misaligned from an intended position, the shape of the dummy metal fill within a region of the gate electrode is kept symmetric with respect to the center of the gate electrode.

REFERENCES:
patent: 6784548 (2004-08-01), Kouno et al.
patent: 2002/0190382 (2002-12-01), Kouno et al.
patent: 2003/0071263 (2003-04-01), Kouno et al.
patent: 2007/0224761 (2007-09-01), Takami
patent: 09-306996 (1997-11-01), None
patent: 2002-373896 (2002-12-01), None
Tuinhout, H.P. et al., “Test Structures for Investigation of Metal Coverage Effects on MOSFET Matching,” Proc. IEEE 1997 Int. Conference on Microelectronic Test Structures, vol. 11, pp. 179-183, Mar. 1997.
Lakshminarayanan, S. et al., “Electrical Characterization of the Coppoer CMP Process and Deviation of Metal Layout Rules,” IEEE Transaction on Semiconductor Manufacturing, vol. 16, No. 4, Nov. 2003.
Lin, Chenting et al., “Planarization of dual-damascene post-metal-CMP structures,” Interconnect Technology, 1999. IEEE International Conference, May 24-26, 1999, pp. 86-88.

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