Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2008-09-18
2010-11-23
Ho, Hoai V (Department: 2827)
Static information storage and retrieval
Floating gate
Particular connection
C365S185050, C257S315000, C257S532000
Reexamination Certificate
active
07839683
ABSTRACT:
The chip area of a semiconductor device including a nonvolatile memory is reduced. The semiconductor device includes a first memory cell and a second memory cell which are formed on the principal surface of a substrate, and arranged adjacent to each other. In a principal surface of the substrate, active regions which are electrically isolated from each other are arranged. In the first active region, the capacitor element of the first memory cell is arranged, while the capacitor element of the second memory cell is arranged in the fourth active region. In the second active region, the respective write/erase elements of the first and second memory cells are both arranged. Further, in the third active region, the respective read elements of the first and second memory cells are both arranged.
REFERENCES:
patent: 2005/0237786 (2005-10-01), Atwood et al.
patent: 2006/0198210 (2006-09-01), Hanzawa et al.
patent: 2007/0058441 (2007-03-01), Oka et al.
patent: 2007-110073 (2007-04-01), None
Akiba Takesada
Oka Yasushi
Omae Tadashi
Ho Hoai V
Miles & Stockbridge P.C.
Renesas Electronics Corporation
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