Semiconductor device

Details Semiconductor device Semiconductor device

2008-06-25

2010-10-12

Coleman, W. David (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Junction field effect transistor

C348S315000

Reexamination Certificate

active

07812377

ABSTRACT:
In the semiconductor device, a gate region is formed in a mesh pattern having first polygonal shapes and second polygonal shapes the area of which is smaller than that of the first polygonal shapes, and drain regions and source regions are disposed within the first polygonal shapes and the second polygonal shapes, respectively. With this configuration, the forward transfer admittance gm can be increased as compared with a structure in which gate regions are disposed in a stripe pattern. Furthermore, compared with a case in which a gate region is disposed in a grid pattern, deterioration in forward transfer characteristics (amplification characteristics) due to an increase in input capacitance Ciss can be minimized while a predetermined withstand voltage is maintained.

REFERENCES:
patent: 6264167 (2001-07-01), Hamazawa
patent: 6740907 (2004-05-01), Sakamoto
patent: 7002192 (2006-02-01), Ku et al.
patent: 7449762 (2008-11-01), Singh
patent: 2006/0255403 (2006-11-01), Asano et al.
patent: 8-227900 (1996-09-01), None
Hatfield, C.W. et al. (1998). “DC I-V Characteristics and RF Performance of a 4H-SiC JFET at 773 K,”IEEE Transactions on Electron Devices. 45.(9):2072-2074.

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