Active solid-state devices (e.g. – transistors – solid-state diode – Bipolar transistor structure – With enlarged emitter area
Reexamination Certificate
2007-12-31
2009-11-10
Louie, Wai-Sing (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Bipolar transistor structure
With enlarged emitter area
C257S578000
Reexamination Certificate
active
07615846
ABSTRACT:
An emitter layer is provided in stripes in a direction orthogonal to an effective gate trench region connected to a gate electrode and a dummy trench region isolated from the gate electrode. A width of the emitter layer is determined to satisfy a predetermined relational expression so as not to cause latch-up in an underlying P base layer. In the predetermined relational expression, an upper limit value of the width W of the emitter layer is (3500/Rspb)·Wso·exp(decimation ratio), where Rspb is a sheet resistance of the P base layer immediately below the emitter layer, Wso is an interval between the trenches, and the decimation ratio is a ratio of the number of the effective gate trench region to the total number of the trench regions. Variations in saturation current in a trench IGBT can be suppressed, and a tolerance of an Reverse Bias Safe Operation Area can be improved.
REFERENCES:
patent: 5623152 (1997-04-01), Majumdar et al.
patent: 6781199 (2004-08-01), Takahashi
patent: 2001-168333 (2001-06-01), None
patent: 2002-100770 (2002-04-01), None
patent: 2005-158850 (2005-06-01), None
Jahan Bilkis
Louie Wai-Sing
Mitsubishi Electric Corporation
Oblon, Spivak McClelland, Maier & Neustadt, L.L.P.
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