Semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – Having specific type of active device

Reexamination Certificate

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Details

C257S206000, C257S202000

Reexamination Certificate

active

07456446

ABSTRACT:
A semiconductor device of the generation with the minimum processing dimensions of 90 nm, or later, wherein variation of processing dimensions of gate electrodes in a logic block and a power source noise are suppressed; wherein a gate electrode formed to have a comb-shaped pattern is formed on a normal cell region, a dummy gate electrode formed to have a comb-shaped pattern is formed on a vacant region, a wiring for applying a predetermined voltage is connected respectively to at least a part of the dummy gate and the semiconductor substrate (source drain regions), and an electrostatic capacity between the part of the dummy gate electrode and the semiconductor substrate constitutes a decoupling capacitor of the power source.

REFERENCES:
patent: 6020616 (2000-02-01), Bothra et al.
patent: 6516457 (2003-02-01), Kondou
patent: 6707107 (2004-03-01), Kido
patent: 2001/0004122 (2001-06-01), Ito
patent: 2003/0132464 (2003-07-01), Yamaguchi et al.
patent: 2004/0213029 (2004-10-01), Hirata et al.

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