Semiconductor device

Coded data generation or conversion – Digital code to digital code converters – Serial to parallel

Reexamination Certificate

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Details

C341S101000

Reexamination Certificate

active

07369069

ABSTRACT:
A semiconductor device including a clock signal generation circuit and a plurality of circuit blocks operating in synchronization with the clock signal, in which each of the plurality of the circuit blocks conducts resetting treatment receiving the interruption signal reset_in outputted in synchronization with the clock signal in the course of frequency acquisition, whereby the timing margin is improved greatly to facilitate the design of timing for a case of conducting interruption between a plurality of circuit blocks operating at high speed simultaneously and decrease circuit scale and power consumption.

REFERENCES:
patent: 4882762 (1989-11-01), Waldhauer
patent: 7064690 (2006-06-01), Fowler et al.
patent: 7116251 (2006-10-01), Groen et al.
patent: 7200832 (2007-04-01), Butt et al.
patent: 07-046143 (1995-02-01), None

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