Semiconductor device

Details Semiconductor device Semiconductor device

2008-01-15

2008-01-15

Sherry, Michael (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C326S030000

Reexamination Certificate

active

11288323

ABSTRACT:
This invention provides a semiconductor device in which an ESD protection circuit and a termination circuit can be realized with a small die area. A PMOS transistor having an ESD protection function is placed between a signal node on a line from an signal terminal to an input buffer and a supply voltage node. Furthermore, a voltage generator circuit is placed to supply a reference voltage to the gate of the PMOS transistor. By the reference voltage controlled by the voltage generator circuit, a source drain resistance of the PMOS transistor is set. Thereby, the PMOS transistor can be made to function as a terminating resistor whose resistance can be set adaptively to a characteristic impedance of a transmission line, for example, connected to the signal terminal in addition to the ESD protection function.

REFERENCES:
patent: 5615073 (1997-03-01), Fried et al.
patent: 6181157 (2001-01-01), Fiedler
patent: 6353334 (2002-03-01), Schultz et al.
patent: 6424169 (2002-07-01), Partow et al.
patent: 2002/0014904 (2002-02-01), Morishita
patent: 2002-050698 (2000-08-01), None

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