1989-03-13
1990-10-16
Clawson, Joseph E.
357 43, 357 38, 357 90, H01L 2702
Patent
active
049639730
ABSTRACT:
A semiconductor device has a well region formed in the surface of a substrate, and has semiconductor elements such as MOSFETs and bipolar transistors formed in the well region. The carrier concentration profile of the well region assumes the shape of a valley in the direction of depth thereof, and a minimum point thereof has a concentration of smaller than 5.times.10.sup.15 cm.sup.-3 and is located at a position within 1.6 .mu.m from the surface of the substrate. Preferably, the minimum point should have a concentration of greater than 5.times.10.sup.14 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3, and more preferably a concentration of greater than 1.times.10.sup.15 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3.
REFERENCES:
patent: 4032372 (1977-06-01), Vora
patent: 4247862 (1981-01-01), Klein
patent: 4604790 (1986-08-01), Bonn
J. Borland et al., "Advanced CMOS Epitaxial Processing for Latch-Up Hardening and Improved Epilayer Quality", Solid-State Technology, Aug. 1984, pp. 123-131.
Hiraishi Atsushi
Ikeda Takahide
Minami Masataka
Momma Naohiro
Nagano Takahiro
Clawson Joseph E.
Hitachi , Ltd.
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