Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2007-10-23
2007-10-23
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Interconnection arrangements
C365S051000, C365S052000, C257S777000, C257S784000, C257S786000
Reexamination Certificate
active
11401284
ABSTRACT:
A semiconductor device uses a package substrate on which bonding leads are formed respectively corresponding to bonding pads for address and data which are distributed to opposing first and second sides of a memory chip and address terminals and data terminals which are connected to the bonding leads. The semiconductor device further includes an address output circuit and a data input/output circuit which also serves for memory access and a signal processing circuit having a data processing function. A semiconductor chip having bonding pads connected to the bonding leads corresponding to the address terminals of the package substrate and bonding pads connected to the bonding leads corresponding to the data terminals of the package substrate and distributed to two sides out of four sides and the above-mentioned memory chip are mounted on the package substrate in a stacked structure. Bonding leads arranged along at least one side of the substrate may include bonding leads of rectangular configuration having longer sides disposed at acute angles with respect to the side of the substrate.
REFERENCES:
patent: 4442507 (1984-04-01), Roesner
patent: 4962415 (1990-10-01), Yamamoto et al.
patent: 6365966 (2002-04-01), Chen et al.
patent: 7061785 (2006-06-01), Miwa et al.
patent: 2002-043531 (2002-02-01), None
Hashizume Takanori
Ichitani Masahiro
Kudo Ikuo
Miwa Takashi
Morino Naozumi
Miles & Stockbridge P.C.
Renesas Technology Corp.
Tran Andrew Q.
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