Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame
Patent
1998-07-28
1999-12-07
Clark, Shiela V.
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
257723, 257724, 257677, H01L 23495
Patent
active
059988568
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
The present invention relates to a semiconductor device, and more particularly, it relates to a semiconductor device packaging power devices and a control device controlling these power devices.
BACKGROUND TECHNIQUE
FIG. 6 shows a semiconductor device described in Japanese Patent Laying-Open Gazette No. 5-299576. The semiconductor device 90 shown in FIG. 6 has a structure of storing power devices and IC-ed control devices controlling these power devices in the same package, and is called a multi-chip type semiconductor device.
In FIG. 6, external leads 23 having power chip mounting regions 23a for mounting power chips 26 and control chip mounting regions 33a mounting control chips 27 extend from oppositely arranged two lead frames 31.
The power chips 26 and the control chips 27 are electrically connected with the external leads extending from the lead frames 31 by aluminum wires 28 and gold wires 29 respectively. It comes to that the power chips 26 and the control chips 27 are sealed with outer packaging resin 101 which is formed on a region enclosed with one-dot chain lines shown in FIG. 6.
At this point, electrical connection between the power chips 26 and the control chips 27 and the external leads is performed by wire bonding. In the wire bonding, reliable bonding cannot be performed unless the material for the wires and the material for the parts to which these wires are connected are properly combined with each other.
Namely, at least connecting portions must be of nickel in the external leads connecting the aluminum wires 28, and at least connecting portions must be of silver in the external leads connecting the gold wires 29. Since the lead frames 31 are made of copper in general, nickel plating and silver plating have been performed on the parts to which the aluminum wires 28 and the gold wires 29 are connected.
At this point, the parts to which the aluminum wires 28 and the gold wires 29 are connected have been intermixed with each other as shown in FIG. 6, and hence nickel plating and silver plating have been performed by spot plating locally performing plating.
In order to perform spot plating, a copper plate serving as the material is worked by punching for forming a lead frame and thereafter covering a part not to be plated with a mask for performing plating only on an opening part, while the shape of the mask is complicated and a step of sticking the mask to the lead frame is troublesome, and hence there have been such problems that workability of assembly is inferior and the assembly, cost is high.
As shown in FIG. 6, the power chip mounting regions 23a and the control chip mounting regions 33a have been in structures connected to the lead frames 31 in single directions. Therefore, the same are in cantilevered states and readily deformed if excess force is applied, and hence there have been such problems that bonding operations for the power chips 26 and the control chips 27 and an operation for transporting the lead frames 31 after wire-bonding the aluminum wires 28 and the gold wires 29 are not easy, operability is inferior and the assembly cost is high. In recent years, enlargement of an IPM progresses, and particularly power chips enlarge and the weight also tends to get heavy. In such circumstances, it prompts the aforementioned problems that the power chip mounting regions and the control chip mounting regions, particularly the power chip mounting regions are in cantilevered structures, and hence becomes an important subject.
Thus, in the conventional semiconductor device, there have been such problems that workability of assembly is inferior since spot plating has been performed in the connecting portions in case of connecting the aluminum wires and the gold wires with the external leads, and the assembly cost is high.
Further, the power chip mounting regions and the control chip mounting regions have been in cantilevered states, and hence there have been such problems that workability of assembly is inferior and the assembly cost is high.
DISCLOSURE OF THE INVE
REFERENCES:
patent: 5598038 (1997-01-01), Sugano
patent: 5767567 (1998-06-01), Hu et al.
patent: 5767573 (1998-06-01), Noda et al.
Iwagaki Seiki
Iwagami Tooru
Kawafuji Hisashi
Noda Sukehisa
Yamada Shinji
Clark Shiela V.
Mitsubishi Denki & Kabushiki Kaisha
LandOfFree
Semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-827006