Semiconductor device

Static information storage and retrieval – Format or disposition of elements

Reexamination Certificate

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C365S063000, C257S691000

Reexamination Certificate

active

11135297

ABSTRACT:
A wiring board includes a plurality of wiring layers, and one surface formed with a plurality of chip connecting electrodes and another surface formed with a plurality of external connecting electrodes of a semiconductor device. The wiring board has wiring layers and vias. The plurality of chip connecting electrodes include first chip connecting electrodes, each used for a first signal whose logic value changes, and second chip connecting electrodes, each used for a second signal that changes after a change timing of the first signal. A wiring layer in which wiring routing of paths extending from the first chip connecting electrodes to their corresponding first external connecting electrodes is performed, and a wiring layer in which wiring routing of paths extending from the second chip connecting electrodes disposed adjacent to the first chip connecting electrodes to their corresponding second external connecting electrodes is performed, are made different from each other.

REFERENCES:
patent: 6545895 (2003-04-01), Li et al.
patent: 6803659 (2004-10-01), Suwa et al.
patent: 6815746 (2004-11-01), Suzuki et al.
patent: 6967368 (2005-11-01), Ozaki et al.
patent: 2005/0104175 (2005-05-01), Itano et al.
patent: 2006/0103004 (2006-05-01), Sakai et al.
patent: 07-283340 (1995-10-01), None
patent: 11-097613 (1999-04-01), None
patent: 2003-036700 (2003-02-01), None

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