Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular chip input/output means
Reexamination Certificate
2007-01-30
2007-01-30
Huynh, Andy (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular chip input/output means
C257S207000, C257S786000, C257SE23079, C257SE23153
Reexamination Certificate
active
10956140
ABSTRACT:
A chip size is remarkably reduced by providing effective layout of the I/O buffers. Since a large capacity non-volatile memory is arranged, bonding pads are arranged at the area near each side of the rectangular shape semiconductor chip and the I/O buffers are arranged in the side of the internal circuit area of these bonding pads. In this semiconductor chip, the number of I/O buffers in the side of the longer sides is larger than that in the side of the shorter sides of the semiconductor chip. For example, the n I/O buffers are arranged respectively in the side of two longer sides, while (n−2) I/O buffers are arranged respectively in the side of two shorter sides. Accordingly, the I/O buffers can be arranged without unnecessary increase in the chip area.
REFERENCES:
patent: 5235207 (1993-08-01), Ohi et al.
patent: 5401989 (1995-03-01), Kikuchi
patent: 6339234 (2002-01-01), Takizawa
patent: 2002-043531 (2002-02-01), None
Huynh Andy
Nguyen Dao H.
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