Static information storage and retrieval – Powering
Reexamination Certificate
2007-01-09
2007-01-09
Zarabian, Amir (Department: 2827)
Static information storage and retrieval
Powering
C327S141000, C327S142000, C327S143000, C327S530000
Reexamination Certificate
active
10994412
ABSTRACT:
A high-density DDR-1/DDR-2 compatible SDRAM chip with a reduced output circuit area is provided. When the SDRAM is a DDR1 SDRAM, an output signal output from an output circuit (14) is output to an output terminal (17) as a main output signal. When the SDRAM is a DDR2 SDRAM, an output signal output from an output circuit (15) is output to the output terminal (17) as the main output signal and, at the same time, the output signal output from the output circuit (14) is output as a sub-output signal to perform operation for adjusting the slew rate or the amount of output current of the main output signal or for adjusting the impedance of the output terminal as viewed from an external point.
REFERENCES:
patent: 6356488 (2002-03-01), Kang
patent: 6366506 (2002-04-01), Mizuno et al.
patent: 6483357 (2002-11-01), Kato et al.
patent: H08-65131 (1996-03-01), None
T. Sakata, et al DDDR/SDR- Compatible SDRAM Design with a Three-size Flexible Column Redunadancy, 2000 Symposium on VLSI Circuits Digest of Technical Paper, IEEE, 2000, p. 116-119.
C. Yoo, et al., “A 1.8V 700 Mb DDR-II SDRAM with On die Termination and Off-Chip Driver Calibration” 2003 IEEE International Sokid State Circuits Conference.
Elpida Memory Inc.
Pham Ly Duy
Sughrue & Mion, PLLC
Zarabian Amir
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