Semiconductor device

Static information storage and retrieval – Addressing – Plural blocks or banks

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Details

365 63, 365 52, G06F 1300

Patent

active

056383355

ABSTRACT:
A memory device comprising a memory array having a plurality of bits, including parity bits, and comprising a plurality of memory blocks, and a bit structure changing section for changing the input/output bits of the memory array, wherein the number of the memory blocks are prescribed to be an integral multiple of three and the input/output bits of the plurality of memory blocks are even. Thereby, the bit structure of the semiconductor memory, having parity bits and which is capable of changing the input/output bits to a plurality of bit structures, can be changed while maintaining the bit structure of the memory blocks even and without increase in propagation delay time.

REFERENCES:
patent: 5228132 (1993-07-01), Neal et al.
patent: 5243570 (1993-09-01), Saruwatari
patent: 5289428 (1994-02-01), Sato

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