Semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame

Reexamination Certificate

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Details

C257S676000, C257S787000

Reexamination Certificate

active

07019388

ABSTRACT:
It is intended to improve the production yield of QFN (Quad Flat Non-leaded package) and attain a multi-pin structure. After a resin sealing member for sealing a semiconductor chip is formed by molding, a peripheral portion of the resin sealing member and a lead frame are both cut along a cutting line which is positioned inside (on a central side of the resin sealing member) of a line (molding line) extending along an outer edge of the resin sealing member, whereby the whole surface (upper and lower surfaces and both side faces) of each of leads exposed to side faces (cut faces) of the resin sealing member is covered with resin, thus preventing the occurrence of metallic burrs on the cut faces of the leads.

REFERENCES:
patent: 5977615 (1999-11-01), Yamaguchi et al.
patent: 6177718 (2001-01-01), Kozono
patent: 6208020 (2001-03-01), Minamio et al.
patent: 6338984 (2002-01-01), Minamio et al.
patent: 6828661 (2004-12-01), Araki et al.
patent: 2002/0121670 (2002-09-01), Minamio et al.
patent: 2003/0015775 (2003-01-01), Minamio et al.
patent: 04133453 (1992-05-01), None
patent: 07176678 (1995-07-01), None
patent: 3072291 (2000-05-01), None
patent: 2001-189410 (2001-07-01), None

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