Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
2005-02-15
2005-02-15
Dang, Phuc T. (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S784000, C257S788000
Reexamination Certificate
active
06856022
ABSTRACT:
According to the invention, in input/output circuit portions positioned around a semiconductor chip, electrode pads are arranged above each of a plurality of input/output cells arranged in a line. The width of the electrode pads is greater than the width of the input/output cells, and thus the electrode pads cannot be arranged in a single line and are instead arranged staggered in two lines. The electrode pads of one row are arranged shifted so that they do not overlap with the internal terminals of the input/output cells, but are disposed near these internal terminals. The spacing between the electrode pads is set to a distance that is at least a set distance determined by the isolation rules of the design.
REFERENCES:
patent: 4992845 (1991-02-01), Arakawa et al.
patent: 4999698 (1991-03-01), Okuno et al.
patent: 61-290747 (1986-12-01), None
patent: 07-37929 (1995-02-01), None
patent: P2000-164620 (2000-06-01), None
patent: P2002-329742 (2002-11-01), None
Doi Atsushi
Nagai Noriyuki
Nojiri Naoki
Takemura Koji
Matsushita Electric - Industrial Co., Ltd.
McDermott Will & Emery LLP
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