Semiconductor device

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings

Reexamination Certificate

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Details

C257S690000, C257S693000, C257S777000

Reexamination Certificate

active

06953991

ABSTRACT:
A semiconductor device comprising a laminate of plural insulating substrates101to104on which are mounted semiconductor chips (electronic parts)12, wherein, when the lower-most insulating substrate is regarded to be a first insulating substrate101and other insulating substrates to be second insulating substrates102to104among the insulating substrates that are laminated;second electrically conducting wirings112to114are so provided as to protrude beyond the peripheral edges of the second insulating substrates and are folded toward the side of other surfaces of the second insulating substrates, and the thus folded second electrically conducting wirings are electrically connected to the electrically conducting wirings on the lower insulating substrates.

REFERENCES:
patent: 5546279 (1996-08-01), Aota et al.
patent: 6239496 (2001-05-01), Asada
patent: 6424031 (2002-07-01), Glenn
patent: 57-12754 (1982-01-01), None
patent: 2-20055 (1990-01-01), None
patent: 02-134859 (1990-05-01), None
patent: 04-085837 (1992-03-01), None
patent: 57-069765 (1992-04-01), None
patent: 05-183103 (1993-07-01), None
patent: 05-211246 (1993-08-01), None
patent: 06-216305 (1994-08-01), None
patent: 07-249725 (1995-09-01), None
patent: 08-051182 (1996-02-01), None
patent: 8-130046 (1996-05-01), None
patent: 8-222691 (1996-08-01), None
patent: 08-306815 (1996-11-01), None
patent: 09-246454 (1997-09-01), None
patent: 11-8331 (1999-01-01), None
International Preliminary Examination Report (PCT/IPEA/409 and PCT/IPEA/416) (translated) issued for PCT/JP01/04656.

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