1976-08-24
1978-03-28
Wojciechowicz, Edward J.
357 22, H01L 2980, H01L 2978
Patent
active
040818179
ABSTRACT:
An insulated gate FET comprises a semiconductor substrate, source and drain regions formed in the surface of the semiconductor substrate in a manner spaced at a prescribed interval from each other, and a gate electrode provided on a surface portion of the substrate between the source and drain regions through an insulation layer. Depletion layers formed by the action of a buit-in-field are spread, respectively, into said semiconductor substrate from the source and drain regions, and these two depletion layers contact each other.
REFERENCES:
patent: 3821776 (1974-06-01), Hayashi et al.
patent: 3828230 (1974-08-01), Nishizawa et al.
patent: 3868274 (1975-02-01), Hubar et al.
Tokyo Shibaura Electric Co. Ltd.
Wojciechowicz Edward J.
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