Semiconductor device

Details Semiconductor device Semiconductor device

2005-05-03

2005-05-03

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S207000, C257S208000, C257S203000, C257S211000, C257S700000, C257S701000, C257S758000, C257S691000, C257S692000, C257S698000, C257S775000

Reexamination Certificate

active

06888254

ABSTRACT:
First and second IP cores are formed on one chip. Each of the first and second IP cores has metal layers. In the first IP core, an uppermost layer of the metal layers is thick and is a layer on which a core power source line is formed. In the second IP core, a metal layers equal in level to the uppermost layer in the first IP core becomes an intermediate layer. In the second IP core, thin intermediate layers are formed on this intermediate layer. Thin intermediate layers are layers on which signal lines are formed and have a narrow wiring pitch. In the second IP core, a layer on which a power source line is formed is provided on the thin intermediate layers.

REFERENCES:
patent: 5488542 (1996-01-01), Ito
patent: 6078100 (2000-06-01), Duesman et al.
patent: 6246112 (2001-06-01), Ball et al.
patent: 6262487 (2001-07-01), Igarashi et al.
patent: 10-173055 (1998-06-01), None
patent: 2000-297670 (2004-06-01), None

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