Semiconductor device

Details Semiconductor device Semiconductor device

2002-09-09

2004-06-01

Eckert, George (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S750000, C257S752000, C257S775000

Reexamination Certificate

active

06744139

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device with gate structures.
2. Description of the Background Art
For semiconductor devices with gate structures, one conventional method of element isolation is the well-known LOCOS (Local Oxidation of Silicon) technique.
FIG. 13
is a cross-sectional view in schematic form illustrating a semiconductor device structure using the LOCOS technique. As shown in
FIG. 13
, a conventional semiconductor device includes a semiconductor substrate
100
, a plurality of MOS transistors
120
(one of which is shown in the drawing) and an interlayer insulation film
102
formed of, for example, silicon oxide film, wherein LOCOS isolation films
101
provide isolation between each of the MOS transistors
120
. In the surface of the semiconductor substrate
100
, a P-type well region
190
, for example, is formed. The MOS transistors
120
each have N-type source/drain regions
103
, for example, spaced at predetermined intervals in the well region
190
and a gate structure
110
formed on the surface of the semiconductor substrate
100
sandwiched between the source/drain regions
103
. The gate structure
110
includes a layered structure
200
in which a gate insulating film
104
, a polysilicon film
106
, a tungsten silicide film
107
and an insulation film
109
are stacked one above another in order from the semiconductor substrate
100
side, and sidewalls
105
formed on the side surfaces of the layered structure
200
. The polysilicon film
106
and the tungsten silicide film
107
form a gate electrode
108
, and the insulation film
109
is formed of, for example, silicon oxide film. The interlayer insulation film
102
is formed on the semiconductor substrate
100
to cover the gate structure
110
and the LOCOS isolation films
101
.
In the above-described semiconductor device, a contact hole
111
is formed in the interlayer insulation film
102
for providing connection between a metal wiring layer (not shown) to be formed on the interlayer insulation film
102
and one of the source/drain regions
103
of the MOS transistor
120
. More specifically, as shown in
FIG. 13
, using a patterned resist
112
formed on the interlayer insulation film
102
as a mask, the interlayer insulation film
102
is selectively dry etched to form the contact hole
111
which extends from the upper surface of the interlayer insulation film
102
to the semiconductor substrate
100
. At this time, if the contact hole
111
is formed out of position, it may extend through the source/drain region
103
to the well region
190
. In this condition, when the contact hole
111
is filled with a metal material and a metal wiring layer is formed on the interlayer insulation film
102
to be connected to the metal material, the metal wiring layer and the well region
190
will be connected to each other.
To prevent such a short between the metal wiring layer and the well region
190
, a method has been adopted for forming, after the formation of the contact hole
111
, a diffusion layer of the same conductivity type as the source/drain regions
103
, in this case a P-type diffusion layer, in the well region
190
appearing in the bottom of the contact hole
111
. This method is called an “SAC (Self-Aligned Contact) implantation method”.
By the way, the aforementioned LOCOS technique could no longer conform to further requirement for device miniaturization from the market and thus, an STI (Shallow Trench Isolation) technique has been adopted as another method of element isolation. In the STI technique, however, even if the SAC implantation method is used to solve the aforementioned problem, it is difficult to form a homogenous P-type diffusion layer in the well region
190
appearing in the bottom of the contact hole
111
, because of a steeply inclined trench formed in the semiconductor substrate
100
for element isolation. To cope with this problem, the method hitherto adopted is, as shown in
FIG. 14
, to form, after the formation of the MOS transistors
120
, a stopper film
115
on the semiconductor substrate
100
to cover the surface of the gate structure
110
of the MOS transistor
120
and then to form the interlayer insulation film
102
on the stopper film
115
. This stopper film
115
is formed of, for example, silicon nitride film and acts as an etch stop when a contact hole is formed in the interlayer insulation film
102
. FIG.
14
and
FIG. 15
which will be described later are cross-sectional views in schematic form illustrating a semiconductor device structure using STI isolation films
113
instead of the LOCOS isolation films
101
in the semiconductor device shown in FIG.
13
.
As shown in
FIG. 14
, in order to provide connection between one of the source/drain regions
103
of the MOS transistor
102
and a metal wiring layer (not shown) formed in the upper part, the interlayer insulation film
102
is first selectively etched using the stopper film
115
as an etch stop to form a contact hole
114
. Then, as shown in
FIG. 15
, the exposed stopper film
115
is selectively etched to form a contact hole
16
, thereby completing the formation of a contact hole
111
which extends from the upper surface of the interlayer insulation film
102
to the semiconductor substrate
100
. The process of forming the contact hole
111
extending from the upper surface of the interlayer insulation film
102
to the semiconductor substrate
100
in this way can be divided into two steps: the step of etching the interlayer insulation film
102
and the step of etching the stopper film
115
, whereby the amount of the semiconductor substrate
100
to be etched by the formation of the contact hole
111
can be reduced. This prevents a short between the upper metal wiring layer and the well region
190
.
To illustrate the above in a concrete form, the amount of overetch when forming a contact hole shall, for example, be 30% of the thickness of a film to be etched. For example, where the interlayer insulation film
102
has a thickness of 500 nm and no stopper film
115
is formed as in the semiconductor device shown in
FIG. 13
, the semiconductor substrate
100
will be etched to a depth of 150 nm from its upper surface, when the contact hole
111
is formed. In this case, the contact hole
111
, if formed out of position, can extend to the well region
190
.
In the semiconductor device with the stopper film
115
as shown in
FIGS. 14 and 15
, on the other hand, although the step of etching the stopper film
115
after etching of the interlayer insulation film
102
must additionally be provided, the thickness of the stopper film
115
is very small as compared with the interlayer insulation film
102
and thus, the amount of the semiconductor substrate
100
to be etched when the contact hole
111
is formed will be less than would be the case where the semiconductor device has no stopper film
115
. To be more specific, where the stopper film
115
has a thickness of 50 nm, the semiconductor substrate
100
will be etched to a depth of only 15 nm from its upper surface when the contact hole
116
is formed. Thus, even if the contact hole
111
is formed out of position, it will not extend to the well region
190
as shown in FIG.
15
.
Next, how, in the semiconductor device shown in
FIGS. 14 and 15
, the source/drain region
103
or the gate electrode
108
of the gate structure
110
is connected to the upper metal wiring layer formed in the interlayer insulation film
102
will be described in more detail with reference to
FIGS. 16
to
20
.
FIGS. 16
to
20
are partial views of the semiconductor device shown in
FIGS. 14 and 15
.
First, as shown in
FIG. 16
, the source/drain regions
103
and the gate structure
110
of the MOS transistor
120
are formed and the stopper film
115
is formed on the semiconductor substrate
100
to cover the surface of the gate structure
110
. Further, the interlayer insulation film
102
is formed on the stopper film
115
and the patterned res

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