Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Amplitude control
Reexamination Certificate
2002-08-02
2004-06-01
Nuton, My-Trang (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Amplitude control
C327S108000
Reexamination Certificate
active
06744298
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor devices and particularly to a configuration of an output circuit driving an external bus signal line in response to an internal signal. More specifically, the present invention relates to a configuration of signal output circuitry of a semiconductor device supplied with an output power supply voltage used for outputting a signal and an external power supply voltage used for driving an internal circuit, separately.
2. Description of the Background Art
FIG. 11
schematically shows a configuration of a main portion of a conventional semiconductor device. The semiconductor device
900
includes an internal power supply circuit
901
generating various kinds of internal voltage from an external power supply voltage EXVDD, a memory circuit
902
operating in accordance with the various kinds of internal voltage generated by internal power supply circuit
901
, and an output circuit
903
receiving an externally supplied output power supply voltage VDDQ as an operating power supply voltage to buffer data read from memory circuit
902
and externally output the data.
Internal power supply circuit
901
generates an internal power supply voltage used by memory circuit
902
as an operating power supply voltage, an intermediate voltage, a reference voltage and others. For the purpose of simplifying the figure, however,
FIG. 11
typically shows a peripheral power supply voltage VDDP generated by internal power supply circuit
901
. Normally, external power supply voltage EXVDD is, for example, not lower than 2.5V and output power supply voltage VDDQ is, for example, 1.8V. When external power supply voltage EXVDD is 2.5V, external power supply voltage EXVDD is used as peripheral power supply voltage VDDP. In this case, an array power supply voltage used by a memory cell array included in memory circuit
902
is generated by down-converting external power supply voltage EXVDD. Peripheral power supply voltage VDDP is indicated so as to distinguish peripheral power supply voltage VDDP from external power supply voltage EXVDD in the description.
Memory circuit
902
includes the memory cell array, a row and column select circuit selecting a memory cell of the memory cell array, an internal data read circuit and others.
By applying output power supply voltage VDDQ exclusively to output circuit
903
, memory circuit
902
can be stably operated with internal power supply voltage VDDP generated from external power supply voltage EXVDD, even if the output power supply voltage VDDQ varies due to an operation of output circuit
903
consuming output power supply voltage VDDQ. Even when multi-bit data DQ is generated to be transferred, memory circuit
902
can be operated stably without affect due to variation of output power supply voltage VDDQ.
Furthermore, with output power supply voltage VDDQ exclusively supplied to output circuit
903
, output circuit
903
can be supplied with an operating power supply voltage with sufficiency, and output circuit
903
can thus be operated in stable manner.
FIG. 12
schematically shows a configuration of a portion of output circuit
903
that is related to outputting of one bit of data. In
FIG. 12
, output circuit
903
includes an NAND circuit
906
receiving internal read data RD read from an internal read circuit
905
included in memory circuit
902
and an output enable signal OEM, a gate circuit
907
receiving internal read data RD and output enable signal OEM, a level conversion circuit
908
converting the amplitude of a signal output from NAND circuit
906
to the level of output power supply voltage VDDQ, a level conversion circuit
909
converting the amplitude of a signal output from gate circuit
907
to the level of external power supply voltage EXVDD, an inverter circuit
910
inverting a signal output from level conversion circuit
909
, and an output buffer circuit
912
driving an output node
920
in response to a signal output from level conversion circuit
908
and a signal output from inverter
910
.
Internal read circuit
905
is included in memory circuit
902
shown in
FIG. 11
, includes a preamplifier circuit and others, and receives peripheral power supply voltage VDDP as an operating power supply voltage and generates internal read data RD having the amplitude of the peripheral power supply voltage VDDP level.
NAND circuit
906
and gate circuit
907
receive peripheral power supply voltage VDDP as an operating power supply voltage. When output enable signal OEM is at a logical low level or L level, NAND circuit
906
outputs a signal of a logical high level or H level. When output enable signal OEM attains an H level, NAND circuit
906
operates as an inverter to invert internal read data RD.
When output enable signal OEM is at L level, gate circuit
907
outputs a signal of the H level and when output enable signal OEM attains the H level, gate circuit
907
operates as a buffer circuit and generates an output signal in accordance with internal read data RD.
Level conversion circuit
908
receives output power supply voltage VDDQ as an operating power supply voltage and level conversion circuit
909
receives external power supply voltage EXVDD as an operating power supply voltage.
Level conversion circuits
908
and
909
simply perform the voltage level (or amplitude) conversion and do not perform conversion in logical level.
Output buffer circuit
912
includes a p-channel MOS transistor (an insulated gate field effect transistor) TP connected between an output power supply node and an output node
920
and having a gate thereof receiving a signal output from level conversion circuit
908
, and an n-channel MOS transistor TN connected between output node
920
and a ground node and having a gate thereof receiving a signal output from inverter circuit
910
.
When output enable signal OEM is at L level, NAND circuit
906
and gate circuit
907
each output a signal of the H level, and level conversion circuit
908
outputs a signal at the output power supply voltage VDDQ level and level conversion circuit
909
outputs a signal at the external power supply voltage EXVDD level. Inverter
910
, receiving external power supply voltage EXVDD as an operating power supply voltage and inverting a signal output from level conversion circuit
909
, outputs a signal of the L level.
MOS transistors TP and TN in output buffer circuit
912
are both turned off and thus output buffer circuit
912
attains an output high impedance state.
When output enable signal OEM attains the H level, NAND circuit
906
operates as an inverter, while gate circuit
907
operates as a buffer circuit. When internal read data RD is at H level, NAND circuit
906
outputs a signal of L level and gate circuit
907
outputs a signal of H level. Thus, level conversion circuit
908
outputs a signal of L level and inverter circuit
910
outputs a signal of L level. Thus, MOS transistors TP and TN in output buffer circuit
912
are turned on and off, respectively. In this state, output node
920
is driven to the output power supply voltage VDDQ level via MOS transistor TP.
When internal read data RD is at H level, NAND circuit
906
outputs a signal of H level and gate circuit
907
outputs a signal of L level. In response, inverter
910
outputs a signal of the external power supply voltage EXVDD level and output buffer circuit
912
has MOS transistors TP and TN turned off and on, respectively, and output node
920
is driven via MOS transistor TN to the ground voltage level. By applying a signal of the external power supply voltage level to the gate of MOS transistor TN via inverter circuit
910
, the current driving capability of MOS transistor TN is increased to quickly discharge output node
920
to the ground voltage level.
FIG. 13
shows an exemplary configuration of level conversion circuit
908
. In
FIG. 13
, level conversion circuit
908
includes an inverter
908
a
receiving a signal SIN output from NAND circuit
906
, an n-channel MOS tran
Matsumoto Junko
Okamoto Takeo
Yamauchi Tadaaki
Nuton My-Trang
Renesas Technology Corp.
LandOfFree
Semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3359436