Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2003-04-30
2004-11-30
Wells, Kenneth B. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S390000
Reexamination Certificate
active
06825700
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device for driving a power device and, more particularly, to a semiconductor device of an integrated circuit MOS structure with high-tension resistance which drives a power device such as an inverter and prevents an on operation of a parasitic transistor, using a bootstrap circuit system.
2. Description of the Prior Art
In a conventional bootstrap diode system, although a bootstrap diode is generally provided outside an IC chip having a high-tension resistance (referred to as “high-tension resistance IC chip” or simply “IC chip”, hereinafter), there has been developed a bootstrap diode system in which the bootstrap diode is mounted on the high-tension resistance IC chip for the purpose of achieving a single chip structure.
The high-tension resistance IC chip of a conventional bootstrap circuit system is described with reference to
FIGS. 27 and 28
.
FIG. 27
is a sectional view showing a conventional bootstrap diode and
FIG. 28
is a conventional schematic circuit structure in which a power device (e.g., power converter) is connected to the high-tension resistance IC chip having the bootstrap diode shown in
FIG. 27
mounted thereon.
The bootstrap system shown in
FIG. 27
includes a bootstrap diode portion
101
and a CMOS region
102
for driving a high-tension side which are mounted on a high-tension resistance IC chip. An n− semiconductor layer
106
is formed on a p− substrate
105
, and a p− well
103
and a p+ type diffusion layer
104
of an interlayer insulating film are provided apart from each other in the n− semiconductor layer
106
.
Thus, a power-supply voltage Vcc can be applied between the p− well
103
and the p+ type diffusion layer
104
and a high-tension diode can be used as a bootstrap diode (D
101
). In addition, the p− substrate
105
on the high-tension resistance IC chip is connected to a ground potential (GND) in general.
Referring to
FIG. 28
, C
1
designates an external bootstrap capacitor (referred to as “an external capacitor” hereinafter). An upper (high-tension side) power transistor T
1
and a lower (low-tension side) power transistor T
2
are connected in series between a high-voltage terminal HV and the ground GND, and the transistors T
1
and T
2
have peculiar substrate diodes D
1
and D
2
, respectively.
As shown in the figure, the high-tension resistance IC includes a high-tension side drive circuit
111
, a low-tension side drive circuit
112
, a level shit circuit
113
, a delay circuit
114
and a bootstrap diode D
101
with a high-tension resistance and the high-tension resistance IC is connected to a power device constituted by the transistors T
1
and T
2
and the like so that the power device is driven.
One terminal of the external capacitor C
1
is connected to a power-supply voltage Vcc through the bootstrap diode D
101
on the IC chip. When an output terminal OUT is maintained approximately at a ground potential under the condition that the lower transistor T
2
is in a conducting (ON) state, a charging current is applied to the external capacitor C
1
and the external capacitor C
1
stores a charged voltage V
1
which is slightly lower than the power-supply voltage Vcc by a voltage drop. Thus, the low-tension side drive circuit
112
is driven by the relatively low power-supply voltage Vcc and the high-tension side drive circuit
111
is driven by the voltage V
1
charged in the external capacitor C
1
.
As described above, according to the high-tension resistance IC chip shown in
FIGS. 27 and 28
, an anode
107
of the bootstrap diode D
101
is connected to the power-supply voltage Vcc through a limiting resistance R
1
, a cathode
108
thereof is connected to a floating supply absolute voltage terminal VB on the high-tension side. The external capacitor C
1
is connected between the floating supply absolute voltage terminal VB on the high-tension side and a floating supply offset voltage terminal VS (i.e., output terminal OUT) on the high-tension side.
In this structure, when the transistor T
2
on the low-tension side, which is an output element of a power converter, turns on, the external capacitor C
1
is charged through the high-tension bootstrap diode D
101
, and the drive circuit
111
on the high-tension side is driven by the voltage V
1
charged in the external capacitor C
1
. Thus, there is provided a system in which it is not necessary to additionally provide a floating power supply on the high-tension side.
As another example of a conventional structure, a charging circuit of bootstrap capacitance is disclosed in the Japanese Patent Laid-Open No.9-65571 (1997) gazette (cf. paragraphs [0009] to [0014],
FIGS. 3
to
5
) (referring to as a patent document 1), in which a device for preventing an ON operation of a parasitic transistor of an integrated LDMOS structure during transition is provided, and an integrated LDMOS transistor which guarantees prevention of integrated device breakdown is employed and timing of a lower power element is synchronized with that of the LDMOS.
However, in the bootstrap circuit system having the bootstrap diode D
101
mounted on the high-tension resistance IC as shown in
FIGS. 27 and 28
, a RESURF structure is provided in order to keep a high voltage of a potential of the anode
107
of the diode D
101
which is higher than that of the p− substrate
105
by the power-supply voltage. In this case, when the power-supply voltage Vcc is applied, a parasitic PNP transistor
109
turns on and a current amplification factor H
FE
of the parasitic PNP transistor becomes large because of a low base ion concentration thereof, resulting in a problem that a very large current flows from the anode
107
toward the p− substrate
105
through the p− well
103
and the n− semiconductor layer
106
.
SUMMARY OF THE INVENTION
The present invention has been made to solve the above problems, and has an object to provide a semiconductor device on an IC chip with a high-tension resistance by employing a bootstrap system in which a parasitic transistor is prevented from turning on and a current consumption of a circuit can be reduced.
More specifically, it is a main object of the present invention to prevent the operation of the parasitic PNP transistor as much as possible by performing roles of high-tension maintaining and charging operations by different elements of which junction is isolated. This is because the high-tension maintaining part is of the n− drift layer although it is of the RESURF structure, and therefore the parasitic PNP transistor is not generated.
In addition, as the semiconductor element for charging, roughly two types such as a diode type and a pch-MOS transistor type are mounted, and in order to prevent the operation of the parasitic PNP transistor as much as possible in either type, a base ion concentration is increased by adding a buried n+ layer so that a current amplification factor H
FE
of the parasitic PNP transistor is reduced.
In order to attain the above object, the present invention provides a semiconductor device for driving a power device. The semiconductor device is comprised of a bootstrap circuit which drives a power element on a low-tension side of the power device and supplies a power supply voltage for a high-tension drive side to a bootstrap capacitor connected between a floating supply absolute voltage terminal of the high-tension drive side and a floating supply offset voltage terminal of the high-tension drive side.
The bootstrap circuit includes at least a chargeable semiconductor element region and a high-tension maintaining potion, wherein junction between the chargeable semiconductor element portion and the high-tension maintaining portion is isolated. The high-tension maintaining portion is comprised of an n− drift layer having n+ layers provided at a high-tension side and at an opening portion in an n− semiconductor layer of a high-tens
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