Semiconductor device

Details Semiconductor device Semiconductor device

2002-04-23

2004-06-15

Nguyen, Tuan H. (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S761000, C257S762000, C257S758000

Reexamination Certificate

active

06750541

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority of Japanese Patent Applications No. 2001-130694, filed in Apr. 27, 2001, and No. 2002-43117, filed in Feb. 20, 2002, the contents being incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, a semiconductor device having a multi-layered wiring structure containing a copper layer wiring and a method of manufacturing the same.
2. Description of the Prior Art
Various semiconductor elements are miniaturized more and more with the progress of the process technology of the semiconductor integrated circuit (LSI). Also, the high density, the increase in layer number, and the reduction in thickness of the wirings in the LSI are making rapid progress, and thus the stress applied to the wirings and the density of the current flowing through the wirings are steadily increased respectively. Accordingly, when the current of the high density flows through the wirings, for example, the breaking phenomenon of the wiring that is called the electromigration (EM) is ready to occur. It is supposed that, the driving force of the electromigration is generated when metallic atoms are moved and diffused owing to the collision of the high-density electron flows. Since the degradation phenomenon by the electromigration becomes still more intense with the miniaturization of the element, the development of the wiring material and the wiring structure, through which the high-density current can be passed and which can achieve the high reliability, is required.
As the wiring in which the electromigration is hard to occur rather than the aluminum wiring, there is the copper wiring.
However, the fine patterning of the copper layer is difficult. As one of the effective approaches for manufacturing the copper wiring, the damascene method that has the steps of forming previously the wiring trench in the insulating film and then burying the copper layer therein is put to practical use. Also, the dual-damascene method that forms simultaneously the via and the wiring by forming the via hole under the wiring trench is known.
Then, an example of steps of forming the via by the damascene method is shown in
FIGS. 1A
to
1
D hereunder.
First, as shown in
FIG. 1A
, an interlayer insulating film
102
is formed on a semiconductor substrate
101
, and a first silicon oxide film
103
and a silicon nitride film
107
are formed on the interlayer insulating film
102
. Then, a first wiring trench
104
is formed in these films
103
,
107
by patterning the first silicon oxide film
103
and the silicon nitride film
107
. Then, a barrier metal layer
105
and a first copper layer
106
are formed sequentially in the first wiring trench
104
and on the silicon nitride film
107
to bury the first wiring trench
104
completely. Then, the first copper layer
106
and the barrier metal layer
105
are polished by the chemical mechanical polishing (CMP) method and removed from the upper surface of the silicon nitride film
107
.
Accordingly, as shown in
FIG. 1B
, the first copper layer
106
left only in the first wiring trench
104
is used as a copper wiring
106
a
. Then, a second silicon oxide film
108
is formed on the silicon nitride film
107
and the copper wiring
106
a
respectively.
Then, as shown in
FIG. 1C
, a via hole
109
is formed on the copper wiring
106
a
by patterning the second silicon oxide film
108
.
Then, as shown in
FIG. 1D
, a second barrier metal layer
110
and a second copper layer
111
are formed in the via hole
109
and on the second silicon oxide film
108
. Then, the second copper layer
111
and the second barrier metal layer
110
are polished by the CMP method and removed from the upper surface of the second silicon oxide film
108
. Then, the second copper layer
111
left in the via hole
109
is used as a via
111
a.
The multi-layered copper wiring structure can be obtained by repeating the formation of the copper wiring and the formation of the via in compliance with above steps.
By the way, as shown in
FIG. 1C
, if the via hole
109
is formed in the second silicon oxide film
108
, the copper wiring
106
a
is exposed from the via hole
109
and exposed directly to the outside air.
As a result, it is possible that the copper wiring
106
a
is contaminated, corroded and oxidized and thus the defective connection between the copper wiring
106
a
and the via
111
a
is caused. As its measure, the process of cleaning the copper wiring
106
a
from the via hole
109
is carried out. In this case, if the aspect ratio of the via hole
109
is increased, it becomes difficult to clean completely the surface of the copper wiring
106
a.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device that is capable of preventing the surface oxidation/corrosion of metal patterns used as the copper wiring or the via and a method of manufacturing the same.
According to the present invention, the cap layer made of the substance with which the electrical resistance on the first metal pattern film becomes smaller than the electrical resistance on the insulating film is formed on the first insulating film and the first metal pattern. The metal pattern is the copper wiring or the copper via, for example.
As the material of such cap layer, there are the zirconium nitride that is chemically stable, its compound, etc. It is preferable that the film thickness should be set to less than 20 nm.
Therefore, when the hole or the trench is formed on the first metal pattern and in the second insulating film formed on the first insulating film, the oxidation, the corrosion, and the contamination of the first metal pattern under the hole or the trench are prevented by the cap layer.
In addition, the second metal pattern formed in the hole or the trench is connected electrically to the first metal pattern via the cap layer. While, since the cap layer acts as the insulating portion on the first insulating film, the patterning of the cap layer can be omitted.
The zirconium, the titanium, the hafnium, the zirconium nitride, or any one of their compounds constituting such cap layer can be selectively etched on the first insulating film by adjusting the etching conditions while leaving on the first metal pattern. As a result, such cap layer may be removed selectively from the upper surface of the first insulating film by the selective etching without the mask, and may be left on the first metal pattern.
If it is intended to prevent surely the copper diffusion from the first metal pattern containing the copper to the insulating film, the second cap layer made of the copper diffusion preventing insulating material may be formed on the cap layer.


REFERENCES:
patent: 5470789 (1995-11-01), Misawa
patent: 5693563 (1997-12-01), Teong
patent: 6339025 (2002-01-01), Liu et al.
patent: 6342444 (2002-01-01), Higashi et al.
patent: 6355559 (2002-03-01), Havemann et al.
patent: 5-129224 (1993-05-01), None

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