Semiconductor device

Details Semiconductor device Semiconductor device

2003-06-06

2004-11-30

Pham, Long (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

C257S676000, C257S735000, C257S784000

Reexamination Certificate

active

06825548

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and more particularly to a technique that can be effectively applied to a high frequency semiconductor amplifying device for use at a high frequency of about 400 MHz or above.
Semiconductor amplifying devices for microwave use have become even higher in applicable frequency and in output over the recent years, and are extensively used in microwave communication equipment as key devices. Especially, metal oxide semiconductor field effect transistors (MOSFETs) are extensively used to meet high frequency and high output requirements, and are keenly demanded to achieve even higher outputs and higher efficiencies. For this reason, high frequency and high output transistors for use in communication equipment need to be greater in element size (gate width) to increase the output power.
However, MOSFETs used in power amplifiers tend to drop in gain and efficiency as their total gate widths are expanded to increase the power outputs. This phenomenon is discussed in, for instance, The Institute of Electronics, Information and Communication Engineers,
Basics of GaAs Field Effect Transistors
(in Japanese), 1992, pp. 195-198.
To solve this problem, there is used a method by which multiple small size MOSFETs are connected in parallel to distribute and synthesize signals and thereby expand the total gate width equivalently. One such circuit is described, for instance, in the Japanese Unexamined Patent Publication No. Hei 8(1994)-172306 (hereinafter referred to as First Art). In the power amplifying circuit disclosed therein, two MOSFETs are connected in parallel, of each of which the gate electrode is connected to an input side distributing circuit and the drain electrode is connected to an output side synthesizing circuit, both by bonding wires.
Among MOSFET devices for base station use, which require large gate widths to achieve an output of hundreds of watts (W), what have come to constitute a mainstream are internally matching circuit type MOSFET devices, each having in the package a circuit for matching the impedance with an external circuit in addition to a MOSFET chip having a large total gate width to achieve a high output without sacrificing high frequency characteristics. Such internally matching circuit type MOSFET devices are discussed, for instance, in Morikawa et al., “High Efficient 2.2-GHz Si Power MOSFETs for Cellular Base Station Applications”, Proc. of 1999
RAWCON,
p. 305-307, August 1999 and K. Inoue et al., “A High Efficiency High Power GaAs Push-Pull FET for W-CDMA Base Stations”, Proc. of 2001
International Symposium on Power Semiconductor Devices & ICs,
Osaka (hereinafter referred to as Second Art). In each of the internally matching circuit type MOSFET devices disclosed therein, a MOSFET chip is provided on a package, and pads for input and output electrodes of the MOSFET chip are connected to an internally matching circuit configured on the package.
While both First and Second Arts cited above use a configuration in which an external circuit is connected to a MOSFET, a method by which the whole of a MOSFET having a large gate width is caused to operate uniformly to prevent its high frequency characteristics from deterioration is disclosed in the Japanese Unexamined Patent Publication No. Hei 11(1999)-238851 (hereinafter referred to as Third Art). According to the technique disclosed therein, the input electrode pads of the MOSFET and the input terminal of the external circuit are connected in parallel to each other by a plurality of bonding wires, and so are the output electrode pads of the MOSFET and the output terminal of the external circuit. The length of the bonding wire is minimized at the center of the wiring array and consistently increased toward each end of the wiring array.
SUMMARY OF THE INVENTION
According to First Art cited above, the problem that the gain and efficiency drop with an increase in the gate width of the MOSFET is addressed by amplifying signals by using bisected MOSFETs, each of a relatively small gate width. This configuration serves to reduce losses suffered in changing the impedance and to prevent the high frequency characteristics of the MOSFETs from deteriorating, and thereby to reduce the deterioration of the high frequency characteristics of the power amplifying circuit. However, according to this First Art, distributing circuits on both the input side and the output side should be large relative to the size of the two divided MOSFETs. As a result, the possibility of reducing the device size is restricted, and it is also difficult to reduce the number of components used. Furthermore, although small divided MOSFETs are used, the whole MOSFETs are not uniformly operating in the high frequency band, making it impossible to enable the MOSFETs to fully realize their performance potential.
The configuration according to Second Art cited above allows matching to be achieved in a wide band with little loss even where the gate width is large and the impedance of the MOSFET is very low, and is effective for changing the impedance with a reduced deterioration of high frequency characteristics. However, this Second Art takes no account of the impedance change in each of the unit MOSFETs constituting the MOSFET device. As a result, as according to First Art discussed above, the whole MOSFET device is not uniformly operating in the high frequency band, making it impossible to enable the MOSFETs to fully realize their performance potential. Moreover, as it requires a circuit for carrying out impedance matching with the external circuit, the possibility of reducing the device size is restricted, and it is also difficult to reduce the number of components used.
Thus, First and Second Arts are not intended to enable the unit MOSFETs constituting the MOSFET device to operate uniformly at a high frequency. Moreover they require a special external circuit, and any attempt to enhance the performance would invite an increased circuit size. Therefore, it is difficult to reduce the size and enhance the performance at the same time, resulting in a failure to enable the MOSFETs to fully realize their performance potential.
Unlike First and Second Arts described above, Third Art is intended to uniformize power transmission over bonding wires by adjusting the lengths of the bonding wires, and thereby to improve the gain of the microwave amplifier, power adding efficiency and distortion characteristics. As compared with First and Second Arts, it has an advantage in size reduction since no special external circuit is added to the microwave amplifier in which the input and output electrodes of the MOSFETs are connected by a plurality each of wires. However, according to this Third Art, the performance potential of MOSFETs is actualized by contriving effective wiring for the connection of the MOSFETs and the external circuit. Where bonding wires are applied for wiring, for instance, they require length adjustment, which complicates the subsequent steps of the manufacturing process. Particularly in a MOSFET device for base station use, which requires an output of hundreds of watts and therefore an extremely large gate width, a voltage drop due to the parasitic resistance of the bonding wires should be prevented and the matching circuit design should be adapted to a drop in the impedance of the device. This requires a vast number of bonding wires, resulting in an increased influence of mutual inductance. For this reason, Third Art which involves adjustment of the lengths of the bonding wires requires a large difference between long and short bonding wires. However, in usual packaging, the minimum spacing (interval) between a MOSFET chip and an element which are connected by bonding wires, and adjustment of the relative lengths of bonding wires requires long bonding wires. This necessitates a large packaging area and therefore invites an increased device size. Even if the semiconductor chip is reduced in size, the area needed for packaging that semiconductor is enlarged, making

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