Active solid-state devices (e.g. – transistors – solid-state diode – Schottky barrier – To compound semiconductor
Reexamination Certificate
2002-10-15
2004-10-19
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Schottky barrier
To compound semiconductor
C257S476000, C257S655000, C257S334000
Reexamination Certificate
active
06806548
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and particularly to a technique which is effectively applicable to a semiconductor device having a power transistor and a Schottky barrier diode (SBD) on one and the same semiconductor substrate.
As a semiconductor device used as a switching device in a power amplifier or a power supply circuit there is known, for example, a power transistor called power MISFET (Metal Insulator Semiconductor Field Effect Transistor). The power MISFET has a structure wherein plural transistor cells comprising fine patterns of MISFETs are connected in parallel to obtain a large power. Power MISFETs called vertical type and horizontal type are known. As to the vertical type, one called a trench gate structure is also known.
MISFET indicates an insulated gate type field effect transistor wherein a gate insulating film (insulating film) is interposed between a channel forming region (semiconductor) and a gate electrode. One wherein the gate insulating film is formed by a silicon oxide film is generally called MOSFET (Metal Oxide Semiconductor Field Effect Transistor). Moreover, one wherein an electric current flows in the thickness (depth) direction of a semiconductor substrate is called a vertical type, while one wherein an electric current flows in the surface direction of a semiconductor substrate is called a horizontal type. Further, one having a channel (conductive passage) of electrons in a channel forming region between source and drain regions (i.e., under a gate electrode) is called n type (or n-channel conductor type), and one having a channel of holes is called p type (or p-channel conductive type). The trench gate structure indicates a gate structure wherein in the interior of a trench formed in one main surface of a semiconductor substrate there is formed a gate electrode through a gate insulating film. As to the power MISFET of the trench gate structure, it is described in Japanese Published Unexamined Patent Application No. Hei 7(1995)-249770 for example.
FIG. 19
is a circuit diagram of a conventional synchronous rectification type DC/DC converter using power MISFETs and
FIG. 20
is a timing chart of a power MISFET for main switch and a power MISFET for synchronous rectification both shown in FIG.
19
. In
FIG. 19
, Q
1
denotes a power MISFET for main switch, Q
2
denotes a power MISFET for synchronous rectification, BD
1
and BD
2
denote body diodes, and SBD denotes a Schottky barrier diode. The body diodes BD
1
and BD
2
are incorporated in the power MISFETs respectively and are connected in parallel with the power MISFETs. The Schottky barrier diode SBD is connected in parallel with the power MISFET Q
2
for synchronous rectification.
In the synchronous rectification type DC/DC converter shown in
FIG. 19
, a period called “Dead time” is set as shown in
FIG. 20
so as to prevent a lead-through current caused by simultaneous turning ON of both Q
1
and Q
2
. In this period there flow an electric current like B in FIG.
19
. In this case, a circuit loss can be decreased by connecting a Schottky barrier diode smaller in forward voltage (VF) than the body diode BD
2
in parallel with the power MISFET Q
2
for synchronous rectification.
The use of the Schottky barrier diode is essential in such a circuit. In this connection, a semiconductor device is disclosed, for example, in Japanese Published Unexamined Patent Application No. Hei 10(1998)-150140 wherein a semiconductor chip with a power MISFET mounted thereon and a semiconductor chip with a Schottky barrier diode mounted thereon are sealed with a single seal member. Further, a semiconductor device with both a power MISFET of the trench gate structure and a Schottky barrier diode mounted on a single semiconductor substrate is disclosed, for example, in Japanese Published Unexamined Patent Application No. Hei 11(1999)-154748.
SUMMARY OF THE INVENTION
In the semiconductor device wherein a semiconductor chip with a power MISFET mounted thereon and a semiconductor chip with a Schottky barrier diode mounted thereon are sealed with a single seal member, an electric connection between the power MISFET and the Schottky barrier diode is made using a bonding wire, so a parasitic inductance increases and the circuit efficiency of a DC/DC converter, etc is deteriorated.
On the other hand, in the semiconductor device with both a power MISFET of the trench gate structure and a Schottky barrier diode mounted on a single semiconductor substrate, the bonding wire for electric connection between the power MISFET and the Schottky barrier diode can be omitted, so it is possible to decrease a parasitic inductance. As a result, it is possible to control the current flowing time in the body diode of the power MISFET and hence possible to greatly decrease the loss of “Dead time” period during operation of the DC/DC converter which is controlled by PWM.
However, having studied the semiconductor device with both a power MISFET of the trench gate structure and a Schottky barrier diode mounted on one and the same semiconductor substrate, the inventor in the present case found out the following problems.
According to the structure of a conventional semiconductor device, plural cells are defined by trenches in one main surface of a semiconductor substrate, and out of the plural cells, transistor cells for the formation of MISFETSs of the trench structure and Schottky cells for the formation of Schottky barrier diodes are arranged in an alternate manner. The width of each Schottky cell and that of each transistor cell are of the same size. If transistor cells and Schottky cells are arranged in an alternate manner, it is necessary that the trench positioned between adjacent transistor cell and Schottky cell be present in a number corresponding to the number of Schottky cells, thus resulting in an increase in a plane size of the semiconductor substrate, i.e., an increase in chip size.
In the transistor device having both power MISFET of the trench gate structure and Schottky barrier diode on one and the same semiconductor substrate, the area of the power MISFET and that of the Schottky barrier diode are determined so as to satisfy characteristics of the power MISFET and VF characteristics of the Schottky barrier diode, which are required by a user. Therefore, it is necessary that the ratio between the area of the power MISFET and that of the Schottky barrier diode be varied freely so as to meet the user's needs, i.e., it is necessary to ensure the freedom of design.
When the power MISFET is OFF, in the bottom portion of the trench formed between a transistor cell and the associated Schottky cell, and on the transistor cell side, there spreads a depletion layer based on pn junction between a drain region and a channel forming region, so that voltage is not directly applied to the gate insulating film. In contrast therewith, in the trench portion adjacent to the Schottky cell, there is not formed a depletion layer based on pn junction, so that voltage is applied directly to the gate insulating film, with consequent lowering in gate breakdown voltage of the power MISFET.
The Schottky barrier diode is formed by bonding a metal electrode to a semiconductor. But because of electric field concentration at an end of the metal bonded portion, there occurs a lowering in breakdown voltage of the Schottky barrier diode.
It is an object of the present invention to provide a technique capable of attaining the reduction in size of a semiconductor device which has a power transistor and a Schottky barrier diode on one and the same semiconductor substrate.
It is another object of the present invention to provide a technique capable of ensuring the freedom of design in a semiconductor device which has a power transistor and a Schottky barrier diode on one and the same semiconductor substrate.
It is a further object of the present invention to provide a technique capable of enhancing the breakdown voltage of a Schottky barrier diode in a semiconductor device which has a power transistor an
Matsuura Nobuyoshi
Nakazawa Yoshito
Shirai Nobuyuki
Miles & Stockbridge P.C.
Nelms David
Renesas Technology Corp.
Tran Mai-Huong
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