Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-12-04
2004-08-31
Le, Thong Q. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
Reexamination Certificate
active
06785165
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device including a nonvolatile memory unit in which data once stored therein can be rewritten and a variable logic unit whose logical functions can be set programmably, and relates to a technique for constructing such semiconductor device, the technique being effective in application to, for example, a microcomputer of a system-on-chip type or a system LSI.
2. Description of the Related Art
A technique for constructing arithmetic circuitry, using a variable logic unit which is called a Field Programmable Gate Array (EPGA) or a Field Programmable Logic Device (FPLD) is described in JP-A No. 111790/1998. A technique for constructing the EPGA, using electrically rewritable nonvolatile storage elements as its storage cells, the elements being used in an EEPROM and a flash memory, is described in “Interface” pp. 67-68, published by CQ Publishing Co., Ltd. (November 2001).
A nonvolatile memory unit using split-gate-type nonvolatile memory cells is widely used for application in mounting with logical devices on a chip. This split-gate-type nonvolatile memory cell consists of two transistor portions: a memory MOS transistor portion for storing data and a selecting MOS transistor portion for selecting the memory transistor portion and retrieving the data therefrom. As publicly known literature in this relation, the technique hereof is described in the proceedings of the 1994 IEEE, VLSI Technology Symposium, pp. 71-72. The structure and operation of the split-gate-type nonvolatile memory cell will be briefly described. The split-gate-type nonvolatile memory cell is composed of a source, drain, floating gate, and control gate. The floating gate is formed in the memory MOS transistor portion and the gate electrode of the selecting MOS transistor portion makes the control gate. The gate oxide layer of the selecting MOS transistor portion is formed by deposition and functions as an electrically insulating layer between the floating gate and the gate electrode of the selecting MOS transistor. For example, to put the memory cell into the writing state, hot electrons are generated by source side injection and the floating gate is injected with charge. To put the memory cell into the erasure state, the charge retained on the floating gate is discharged from the tip of the floating gate toward the control gate. At this time, it is necessary to apply a high voltage of 12 volts to the control gate. The control gate that functions as a discharging electrode is, in essential, the gate electrode of the selecting MOS transistor portion that is used for selecting a read action.
The present inventors studied mounting a nonvolatile memory unit and a variable logic unit together with other components on a chip.
The purpose of mounting the variable logic unit together with a CPU and other components on a chip is to enable prompt reconfiguration to be performed adaptively to change in hardware specifications and functional change to the CPU and part of the peripheral functions. Moreover, the purpose of mounting the nonvolatile memory unit with the CPU on a chip is to store control program and data for the CPU operation into the on-chip memory so that debugging and program version up for CPU version up can be easily performed. The present inventors pursued the easiness of reconfiguring or upgrading the microcomputer and its peripheral functions by closely associating the variable logic unit with the nonvolatile memory unit. As a result, we discovered that it is important to accomplish quicker read access in both the nonvolatile memory unit and the variable logic unit and provide high reliability of functions to be realized by these units.
Once the variable logic unit is set to perform predetermined logic functions, the logic functions are performed through access to the nonvolatile memory unit and the CPU performs data processing through access to the nonvolatile memory unit. Thus, the nonvolatile memory unit that is applied in a mode that it is mounted with logic devices on a chip is especially required to have quicker read access performance. If the variable logic unit is configured with nonvolatile memory cells as its storage cells, the storage cells to function as switch elements are also required to have quicker read access performance.
In the above-mentioned split-gate-type memory cell structure, the gate electrode of the selecting MOS transistor functions as the electrode for erasure also. Thus, the gate insulation layer of the selecting MOS transistor had to have the same thickness as that of a high-voltage-tolerant MOS transistor for controlling the voltage for writing and erasure in order to assure its withstand voltage. Consequently, Gm (mutual conductance) of the selecting MOS transistor must be low, which makes it hard to obtain a sufficiently great current for reading. It was found that the above split-gate-type memory cell of prior art is not suitable for higher speed operation on a lower voltage with the view of quicker read access performance.
In view of functions to be realized by the nonvolatile memory unit and the variable logic unit, the variable logic unit determines a hardware configuration and the functions to be provided by the configuration are determined or adjusted by using the data stored in the nonvolatile memory unit. Thus, it was found that consideration should be taken to improve both the reliability of the data stored in the nonvolatile memory unit and the reliability of logic constitution definition data to be retained by the variable logic unit.
SUMMARY OF THE INVENTION
It is an object of the present invention is to configure a semiconductor device including a nonvolatile memory unit and a variable logic unit mounted on a chip to achieve higher speed operation on a lower voltage.
It is another object of the present invention is to configure a semiconductor device including a nonvolatile memory unit and a variable logic unit mounted on a chip to achieve high reliability of functions to be realized by these units.
It is a further object of the present invention is to provide a semiconductor device that enables reconfiguring or upgrading a CPU and other peripheral functions mounted thereon easily with a high reliability and can meet requirements of higher speed operation on a lower voltage.
The foregoing and other objects and new features of the invention will be apparent from the description herein and the accompanying drawing.
The advantages to be obtained by a typical semiconductor device provided by the present invention disclosed herein will be summarized below.
According to the invention, a nonvolatile memory cell that essentially has a split gate structure composed of a selecting MOS transistor (second MOS transistor) and a memory MOS transistor (first MOS transistor) is provided. The nonvolatile memory cell is constructed such that the dielectric withstand voltage of the gate of the selecting MOS transistor is lower than that of the memory MOS transistor or the physical or electrical thickness of the gate insulation layer of the selecting MOS transistor is thinner than that of a high-voltage-tolerant MOS transistor (fourth MOS transistor). This makes it possible that the selecting MOS transistor has a high Gm. Because of the high Gm, a sufficiently great current for reading can be obtained and quicker read access to the split-gate-type memory cell can be achieved. A semiconductor device of the invention including a nonvolatile memory unit and a variable logic unit can achieve higher speed operation on a lower voltage.
Current for writing is reduced. Moreover, by using MONOS-type nonvolatile memory cells, the semiconductor device of the invention including a nonvolatile memory unit and a variable logic unit can achieve high reliability of functions to be realized by the nonvolatile memory unit and the variable logic unit.
Furthermore, the semiconductor device of the invention enables reconfiguring or upgrading a CPU and other peripheral functions mounted thereon easi
Kawahara Takayuki
Kubo Masaharu
Matsuzaki Nozomu
Sawase Terumi
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