Semiconductor device

Details Semiconductor device Semiconductor device

2003-03-24

2004-10-26

Zweizig, Jeffrey (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

Reexamination Certificate

active

06809565

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority of, Japanese Patent Application No. 2002-249437, filed on Aug. 28, 2002, in Japan, the contents being incorporated herein by reference.
BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to a semiconductor device and, more particularly, to a semiconductor device which outputs a starter sign to initialize an intern circuit.
(2) Description of the Related Art
An intern circuit in a semiconductor device must be initialized at start time to avoid the indefinite state of the intern circuit after the semiconductor device being started. A semiconductor device outputs a starter sign at start time by an intern starter circuit to reset its intern circuit (see Japanese Patent Laid-Open Publication No. 2002-124861, p. 2, FIG. 9, for example).
FIG. 7
is a view showing a starter circuit in a convention semiconductor device. The starter circuit shown in
FIG. 7
is formed in a semiconductor device and initializes an intern circuit by a starter sign. The starter circuit includes transistors Q
9
through Q
11
, inverter circuits Z
11
and Z
12
, and resistors R
5
through R
7
.
The resistors R
5
and R
6
are connected in series between power supply VDD and the ground of the power supply VDD.
The transistor Q
9
is an n-channel MOS transistor. A gate of the transistor Q
9
is connected to a point where the resistors R
5
and R
6
connect. A source of the transistor Q
9
is connected to the ground of the power supply VDD. A drain of the transistor Q
9
is connected to the power supply VDD via the resistor R
7
.
The transistor Q
10
is a p-channel MOS transistor. The transistor Q
11
is an n-channel MOS transistor. Gates of the transistors Q
10
and Q
11
are connected to each other and are connected to the drain of the transistor Q
9
. A source of the transistor Q
10
is connected to the power supply VDD. A drain of the transistor Q
10
is connected to a drain of the transistor Q
11
. A source of the transistor Q
11
is connected to the ground of the power supply VDD.
The inverter circuit Z
11
is connected to the drains of the transistors Q
10
and Q
11
. The input side of the inverter circuit Z
12
is connected to the output side of the inverter circuit Z
11
. Each of the inverter circuits Z
11
and Z
12
inverts and outputs an input sign.
Now, the operation of the starter circuit will be described.
When power is applied to the semiconductor device, the voltage of the power supply VDD rises and voltage at the point where the resistors R
5
and R
6
connect rises. The source-drain area of the transistor Q
9
is in the off state before voltage at the point where the resistors R
5
and R
6
connect rises to the threshold voltage of the transistor Q
9
. Therefore, the voltage (“H” state) of the power supply VDD is input to the gates of the transistors Q
10
and Q
11
and only the source-drain area of the transistor Q
11
goes into the on state. The voltage (“L” state) of the ground of the power supply VDD is input to the inverter circuit Z
11
via the transistor Q
11
. The inverter circuit Z
11
inverts a sign in the “L” state and outputs a sign in the “H” state. The inverter circuit Z
12
outputs a starter sign sttx in the “L” state.
When voltage at the point where the resistors R
5
and R
6
connect rises to the threshold voltage of the transistor Q
9
(when the voltage of the power supply VDD rises to voltage at which the intern circuit can perform norm operation), the source-drain area of the transistor Q
9
goes into the on state. Therefore, the voltage (“L” state) of the ground of the power supply VDD is input to the gates of the transistors Q
10
and Q
11
and only the source-drain area of the transistor Q
10
goes into the on state. The voltage (“H” state) of the power supply VDD is input to the inverter circuit Z
11
via the transistor Q
10
. The inverter circuit Z
11
inverts a sign in the “H” state and outputs a sign in the “L” state. The inverter circuit Z
12
outputs the starter sign sttx in the “H” state. Initialization of the intern circuit in the semiconductor device terminates when the starter sign sttx rises from the “L” state to the “H” state.
As stated above, when the voltage of the power supply VDD rises to predetermined voltage, the starter sign sttx output from the starter circuit shown in
FIG. 7
rises from the “L” state to the “H” state. The intern circuit in the semiconductor device is initialized and then performs norm operation.
By the way, with semiconductor devices the power consumption of which is low, an electric current must be decreased by sever microamperes.
With the convention semiconductor device, however, the voltage of the power supply VDD is supplied to the starter circuit even at norm operation time after initialization of the intern circuit and an electric current flows through the resistors R
5
to R
7
. As a result, power is consumed.
SUMMARY OF THE INVENTION
The present invention was made under the background circumstances as described above. An object of the present invention is to provide a semiconductor device which shuts off at norm operation time power supply voltage input to a starter circuit to reduce power consumption.
In order to achieve the above object, a semiconductor device which initializes an intern circuit is provided. This semiconductor device includes a starter sign generation circuit for outputting a starter sign which initializes an intern circuit on the basis of input power supply voltage, a latch circuit for holding and outputting the starter sign, and a shutoff circuit for shutting off the power supply voltage input to the starter sign generation circuit at the time of the starter sign being output.
The above and other objects, features and advantages of the present invention will become apparent from the following description when taken in conjunction with the accompanying drawings which illustrate preferred embodiments of the present invention by way of example.


REFERENCES:
patent: 5027006 (1991-06-01), Queinnec et al.
patent: 5172012 (1992-12-01), Ueda
patent: 5825220 (1998-10-01), Kinugasa et al.
patent: 6104221 (2000-08-01), Hoon
patent: 6636089 (2003-10-01), Majcherczak et al.
patent: 2002-124861 (2002-04-01), None

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