Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2003-11-03
2004-12-28
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S723000, C257S737000
Reexamination Certificate
active
06836021
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and, more particularly, to a technology which is effective when applied to a multichip module (MCM) in which a plurality of semiconductor chips are mounted on a single wiring substrate or to a multichip package (MCP).
For the achievement of an improved mounting density in a semiconductor device, various multilayer packages have been proposed in which a plurality of semiconductor chips are mounted in three dimensions on a wiring substrate.
In an exemplary case, memory chips and a microcomputer chip are mounted on a wiring substrate to construct a system. Such a package is also termed as a system in package (SiP).
Memory chips include a DRAM (Dynamic Random Access Memory) and a nonvolatile memory (flash memory), which are encapsulated in conjunction with a high-speed microprocessor (MPU: Micro Processing Unit, very-small-size arithmetic processor) in a single resin package. Such an SiP is higher in functionality than a memory module obtained by resin encapsulating a memory chip so that it is in greater demand.
In particular, mobile equipment for communication such as a mobile phone requires a semiconductor device which is multifunctional and smaller in size so that the SiP is suitable for use in such equipment.
For example, Patent Document 1 discloses a semiconductor device in which a chip (
2
C) formed with a high-speed microprocessor is formed above two chips, which are the chip (
2
A) formed with a DRAM and the chip (
2
B) formed with a flash memory.
[Patent Document 1] International Publication No. WO 02/103793 A1 (FIG. 2)
SUMMARY OF THE INVENTION
The present inventors have developed a multichip module (MCM) in which a plurality of semiconductor chips (hereinafter simply referred to as chips) are embedded in a single package.
The present inventors have examined a multichip module in which a chip formed with a DRAM, a chip formed with a flash memory, and a chip formed with a high-speed microprocessor (MPU) are encapsulated in a single resin package.
In mounting the foregoing three chips on a wiring substrate, the resulting MCM is increased disadvantageously in size if all the chips are mounted in juxtaposed relation so that the present inventors have examined an MCM in which the three chips are mounted in a multilayer structure.
However, there may be a case where the MCM is unintentionally increased in size if a chip formed with a high-speed microprocessor having a large number of pins because of its multifunctionality is disposed in an upper layer as disclosed in Patent Document 1 mentioned above. This is because a sufficiently large wire-to-wire spacing (spacing between bonding pads on a wiring substrate) should be provided when an upper-layer chip and the wiring substrate are connected to each other by wire bonding.
Thus, in the case of stacking a plurality of chips in layers, it is not only important to perform placement by considering the sizes of the chips positioned at the upper and lower levels but also necessary to assemble the chips into a finished MCM which is small in size by considering the characteristics of the individual chips (including pin count and pin arrangement).
In a structure in which an upper-level chip protrudes from (overhangs) the end portion of a lower-level chip, a mold resin is less likely to be filled in the portion underlying the overhanging portion so that an air pool (void) is likely to be formed. If the thermal expansion of the air in the void is repeated during a heat load test, e.g., the delamination between a mold resin and the chip or the cracking of the mold resin (package crack) occurs.
It is therefore an object of the present invention to provide a multichip module having a plurality of chips which is smaller in size or higher in mounting density.
Another object of the present invention is to provide a multichip module having a plurality of chips which has been improved in reliability.
Still another object of the present invention is to provide a multichip module having a plurality of chips which has been improved in functionality.
The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.
A brief description will be given to the outline of the representative aspects of the present invention disclosed in the present application.
In one aspect, a semiconductor device according to the present invention comprises: (a) a wiring substrate having a first surface and a second surface opposing the first surface, first pads being formed over a first region of the first surface, while second pads being formed over a second region surrounding the first region; (b) a microcomputer chip having bump electrodes formed over a surface thereof, the microcomputer chip being mounted over the first region of the wiring substrate such that the first pads and the bump electrodes are electrically connected to each other; and (c) a memory chip having third pads formed over a surface thereof, the memory chip being mounted over a back surface of the microcomputer chip, the third pads being connected to the second pads by use of conductive wires.
In another aspect, the semiconductor device according to the present invention comprises: (a) a wiring substrate having a first surface and a second surface opposing the first surface, first pads being formed over a first region of the first surface, while second pads being formed over a second region surrounding the first region; (b) a microcomputer chip having bump electrodes formed over a surface thereof, the microcomputer chip being mounted over the first region of the wiring substrate such that the first pads and the bump electrodes are electrically connected to each other; and (c) first and second memory chips mounted over a back surface of the microcomputer chip, (c
1
) the first memory chip having third pads formed over a surface thereof, (c
2
) the second memory chip having fourth pads formed over a surface thereof, (c
3
) the third and second pads being connected to the second pads by use of conductive wires.
In still another aspect, the semiconductor device according to the present invention comprises: (a) a wiring substrate having a first surface and a second surface opposing the first surface, first pads being formed over a first region of the first surface, while second pads being formed over a second region surrounding the first region; (b) a microcomputer chip having bump electrodes formed over a surface thereof, the microcomputer chip being mounted over the first region of the wiring substrate such that the first pads and the bump electrodes are electrically connected to each other; and (c) a plurality of memory chips mounted over a back surface of the microcomputer chip, each of the memory chips having third pads formed over a surface thereof, the third pads being connected to the second pads by use of conductive wires.
REFERENCES:
patent: 6740980 (2004-05-01), Hirose
patent: WO 02/103793 (2002-12-01), None
Hayashi Yoshinari
Ishikawa Toshikazu
Kuroda Hiroshi
Naito Takahiro
Ho Tu-Tu
Miles & Stockbridge P.C.
Nelms David
Renesas Technology Corp.
LandOfFree
Semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3287702