Semiconductor device

Details Semiconductor device Semiconductor device

2001-07-12

2004-10-19

Sircus, Brian (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

With specific current responsive fault sensor

Reexamination Certificate

active

06807038

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, it relates to a power semiconductor device having a protective function.
2. Description of the Background Art
FIG. 8
is a block diagram showing the structure of an inverter module
90
having a three-phase bridge circuit. As shown in
FIG. 8
, sets of transistors
11
and
12
, transistors
21
and
22
and transistors
31
and
32
which are power devices such as IGBTs (insulated gate bipolar transistors) are totem-pole connected between terminals P and N, i.e. a high-potential side main power supply terminal P and a low-potential side main power supply terminal N. The main power supply terminals P and N are connected to positive and negative electrodes of a dc power source PS respectively.
Nodes
161
,
162
and
163
between the totem-pole connected transistors
11
and
12
,
21
and
22
and
31
and
32
are connected to output terminals U, V and W of U-, V- and W-phases respectively.
Freewheel diodes
111
,
121
,
211
,
221
,
311
and
321
are connected in antiparallel with the transistors
11
,
12
,
21
,
22
,
31
and
32
respectively.
Packaged control circuits IC
1
, IC
2
and IC
3
are arranged for controlling the sets of the transistors
11
and
12
,
21
and
22
and
31
and
32
respectively. The control circuits IC
1
to IC
3
, which are functionally identical to each other, are shown with different reference numerals for the purpose of convenience.
Control signal output terminals HO and NO of the control circuit IC
1
supply control signals to gate electrodes of the transistors
11
and
12
respectively, control signal output terminals HO and LO of the control circuit IC
2
supply control signals to gate electrodes of the transistors
21
and
22
respectively, and control signal output terminals HO and LO of the control circuit IC
3
supply control signals to gate electrodes of the transistors
31
and
32
respectively.
Standard potential terminals V
S
of the control circuits IC
1
to IC
3
are connected to the nodes
161
,
162
and
163
respectively as well as to standard potential terminals V
UFS
, V
VFS
and V
WFS
of the packages respectively.
Further, standard potential terminals VNO of the control circuits IC
1
to IC
3
are connected to the low-potential side main power supply terminal N in common, while driving voltage terminals V
B
of the control circuits IC
1
to IC
3
are connected to driving voltage terminals V
UFB
, V
VFB
and V
WFB
of the packages respectively.
Each standard potential terminal V
S
supplies a high-potential side reference potential to each control circuit, and each standard potential terminal VNO supplies a low-potential side reference potential to each control circuit.
The control circuits IC
1
to IC
3
have driving voltage terminals V
CC
, ground terminals COM, control signal input terminals PIN and NIN and fault terminals F
O
. The control circuits IC
1
to IC
3
further have current detection terminals CIN
1
, CIN
2
and CIN
3
respectively. The current detection terminals CIN
1
to CIN
3
are functionally identical to each other.
The driving voltage terminals V
CC
of the control circuits IC
1
to IC
3
are connected to driving voltage terminals V
NI
of the module
90
, while the ground terminals COM are connected to a ground terminal V
NC
of the module
90
.
The control signal input terminals PIN of the control circuits IC
1
to IC
3
are connected to control signal input terminals U
P
, V
P
and W
P
of the module
90
respectively, while the control signal input terminals NIN are connected to control signal input terminals U
N
, V
N
and W
N
of the module
90
respectively.
The fault terminals F
O
of the control circuits IC
1
to IC
3
are connected with each other in the module
90
, and connected to a fault terminal FO of the module
90
in common.
The current detection terminal CIN
3
of the control circuit IC
3
is connected to a current detection circuit CIN of the module
90
, and connected to the current detection terminals CIN
1
and CIN
2
in the module
90
.
The ground terminal V
NC
and the current detection terminal CIN of the module
90
are connected to both ends of a shunt resistor R
20
detecting a direct current flowing across the main power supply terminals P and N in the exterior of the module
90
, for detecting the voltage of the shunt resistor R
20
.
The structure for detecting the voltage with the current detection terminals CIN
1
to CIN
3
is now described with reference to FIG.
9
. While
FIG. 9
illustrates the current detection terminal CIN
1
, this structure also applies to the current detection terminals CIN
2
and CIN
3
.
Referring to
FIG. 9
, the voltage of the shunt resistor R
20
detected by the current detection terminal CIN
1
is input in a comparator C, which in turn compares this voltage with a reference voltage REF. If the voltage of the shunt resistor R
20
is in excess of the reference voltage REF, the voltage is supplied through a latch circuit C
2
to a fault circuit C
3
, which in turn supplies an instruction for stopping operation of the transistors
11
and
12
to a power device driving circuit (not shown) provided in the control circuit IC
1
. The fault terminal F
O
outputs the aforementioned instruction.
The inverter module
90
having the aforementioned structure performs dc-ac conversion by alternately driving the transistors
11
,
12
,
21
,
22
,
31
and
32
for supplying ac power to a load (not shown).
When an abnormal current flows across the terminals P and N due to abnormal operation of the transistors
11
,
12
,
21
,
22
,
31
and
32
or the like in the inverter module
90
, the shunt resistor R
20
exhibits an abnormal voltage. The current detection terminals CIN
1
, CIN
2
and CIN
3
of the control circuits IC
1
to IC
3
detect this abnormal voltage and the control circuits IC
1
to IC
3
stop the control signals to the transistors
11
,
12
,
21
,
22
,
31
and
32
respectively, thereby protecting the transistors
11
,
12
,
21
,
22
,
31
and
32
.
Thus, the module
90
requires wires (internal wires) therein for supplying the voltage of the shunt resistor R
20
to all control circuits IC
1
to IC
3
. Consequently, the internal wires are so disadvantageously complicated that the module
90
cannot be miniaturized.
SUMMARY OF THE INVENTION
According to a first aspect of the present invention, a semiconductor device comprises at least one set of complementarily operating first and second switching elements serially interposed between first and second main power supply terminals supplied with a dc voltage, at least one control circuit driving/controlling the set of first and second switching elements and a shunt resistor detecting a current flowing across the first and second main power supply terminals, while the control circuit comprises at least one current detection circuit detecting a voltage generated by a current flowing to the shunt resistor and outputting a current abnormality signal indicating current abnormality when the detected voltage is in excess of a prescribed level and a fault circuit receiving the current abnormality signal output from the current detection circuit and outputting a stop signal for stopping operation of at least one of the first and second switching elements, and the fault circuit has a function of outputting the stop signal to the exterior of the control circuit while stopping operation of at least one of the first and second switching elements also by a signal, identical to the stop signal, input from the exterior of the control circuit.
In the semiconductor device according to the first aspect, the fault circuit has the function of outputting the stop signal to the exterior of at least one control circuit and receiving the signal identical to the stop signal input from the exterior of at least one control circuit for stopping the operation of at least one of the first and second switching elements. Therefore, when at least one set of first and second switch

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