Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For plural devices
Reexamination Certificate
2002-05-20
2004-05-11
Thai, Luan (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
For plural devices
C257S724000, C257S784000
Reexamination Certificate
active
06734553
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a multichip module (referred to as MCM hereinafter) semiconductor device formed by mounting, within the same package, a plurality of electronic components including semiconductor integrated circuit chips (referred to as IC chips hereinafter) into which desired functions are incorporated.
2. Description of the Prior Art
In order to achieve further downsizing, weight reduction, thin forming and high performance for various kinds of apparatus employing a semiconductor device, high density packaging of various kinds of electronic component including IC chips has been investigated. As one of powerful means for achieving the objective there have been proposed various kinds of MCM semiconductor devices having a plurality of IC chips in the same package.
For example, a thin MCM package realizing a multichip semiconductor device with excellent heat dissipation has been proposed in Japanese Patent Applications Laid Open, No. Hei 8-250652, and an MCM semiconductor device aiming at low cost by employing a package that can be used universally even for different kinds or layouts of the IC chips to be mounted is proposed in Japanese Patent Applications Laid Open, No. Hei 9-181256.
FIGS. 7A and 7B
show schematic sectional views of examples of semiconductor devices using an MCM package disclosed in Japanese Patent Applications Laid Open, No. Hei 8-250652.
FIG. 7A
shows a diagrammatic drawing of a first example of MCM package
710
. A printed wiring (PW) board
711
having a large number of level sections consists of a lower level section
712
, an intermediate level section
713
and an upper level section
714
. In this example, the lower level section
712
is continuous, whereas the intermediate and upper level sections respectively have through openings by means of which stepwise openings
715
are formed, and the stepwise openings form a cavity section
716
together with the lower level section
712
.
An MCM tile is a silicon-on-silicon MCM tile
717
consisting of a silicon substrate
718
and silicon chips
719
and
720
, and is situated in the cavity. The silicon substrate has a form in which it is placed in the cavity section on the surface of the lower level section of the PW board. Each of wire bond fingers
721
is interconnected to a contact pad
723
on the intermediate level section of the PW board via a wire
722
.
In turn, each of these pads is interconnected to a part of another level section of the PW board, for example, a contact
725
via a through hole
724
, thereby is interconnected to a solder bump
726
on the bottom face of the lower level section, and is interconnected as needed to another chip or an electronic device such as that represented by a symbol
727
or
728
on the surface of the upper level section of the PW board. Here, the MCM tile placed on the surface of the lower level section is located completely within the cavity section
716
, and the top faces of the chips are at heights lower than the top face of the upper level section of the PW board.
An encapsulation sealing material
729
having high adaptability such as silicone gel is filled in the cavity section
716
. The encapsulation sealing material
729
encapsulates the interconnecting sections between the chips and the silicon substrate, and the wire bond fingers on the silicon substrate, as well as the interconnection sections between the contact pads on the PW board, and the wires interconnecting the wire bond fingers and the contact pads.
In addition, a structural member
730
which acts as a heat sink and encapsulates the cavity section is provided in the device
710
. The end parts
731
of the structural member (heat sink) are situated on the upper level section of the PW board. Although the heat sink is located with a spacing from the chips of the MCM tile, it is situated close to the MCM tile to such a degree that it is sufficient to collect heat generated by the constituent elements of the MCM tile during the operation of the device. As an option, a heat conductive adaptive member
732
such as a heat conductive paste or a thermal grease may be given so as to make physical contact with the chips and the heat sink.
A second example of MCM package
770
is shown in FIG.
7
B. This is an example of an MCM tile having a constitution in which it is interconnected to the PW board by solder reflow bonding. The MCM package has a PW board
771
formed of a single level section which has a through opening
772
. The positional relation between the PW board
771
and an MCM tile
717
is such that chips
719
and
720
of the MCM tile are within the opening
772
, while the end parts of a silicon substrate
718
of the MCM tile are positioned to overlap with the bottom face of the PW board
771
adjacent to the opening so as to have the silicon substrate
718
of the MCM tile to be on the outside of the opening.
Each of bond fingers
773
on the silicon substrate is connected electrically to a contact
774
on the PW board by solder reflow interconnection. A cup-shaped cover
775
makes contact with the bottom face of the silicon substrate
718
while the flanges
776
of the cover are attached to the bottom of the PW board
771
by means of an adhesive (not shown). In order to use the cup-shaped cover as a heat sink for the MCM tile, it is formed of a metal such as copper or a plastic having a high heat conductive property. In the case of a metallic cover, it has an advantage that it acts as a shielding body against electromagnetic radiation.
A cavity section
777
is formed by the wall sections of the opening
772
and the cup-shaped cover, an encapsulation sealing material with adaptability such as silicone gel is filled partially, and the sealing material
729
seals and protects the interconnection part between the MCM tile and bond fingers, and the contacts.
The conventional MCM semiconductor device has a configuration in which a plurality of IC chips are mounted on a silicon substrate being an intermediate substrate, and the silicon substrate is mounted on a PW board, as described, for example, in the semiconductor device disclosed in Japanese Patent Applications Laid Open, No. Hei 8-250652. Accordingly, the size of the silicon substrate becomes extremely large compared with the size of the IC chips, but no consideration on their size is given there. However, in the configuration in which a silicon substrate is adhered to the entire surface of the PW board, as in the example shown in
FIG. 7A
, for example, there occurs a problem that the silicon substrate tends to have cracks due to thermal stress when the size of the silicon substrate is increased. Moreover, wirings mutually connecting the IC chips are formed on the silicon substrate along with the wirings for external connection. For a size of the silicon substrate which exceeds, for example, 20 mm×20 mm, there arises a limit at present in the refinement of a connection wiring pattern because it is impossible to form a wiring pattern in one time of exposure treatment, bringing about also a problem that restricts the realization of higher density for the connection wirings.
Now, by forming an opening in a PW board for mounting an intermediate substrate to accommodate IC chips mounted on the intermediate substrate in the opening, and connects the intermediate substrate to the PW board using only the electrode section provided in the periphery of the intermediate substrate, as in the example in FIG.
7
B and the semiconductor device disclosed in Japanese Patent Applications Laid Open, No. Hei 9-181256, the problem of cracks in the intermediate substrate due to thermal stress can be relaxed. However, since a large opening is provided in the central part of the PW board, there still arises another problem that the number of external connection electrodes of the semiconductor device is limited or that it is necessary to enlarge the size of the PW board in order to secure a prescribed number of electr
Katten Muchin Zavis & Rosenman
NEC Electronics Corporation
Thai Luan
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