Semiconductor device

Details Semiconductor device Semiconductor device

2003-06-19

2004-07-27

Cuneo, Kamand (Department: 2827)

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

With structure for mounting semiconductor chip to lead frame

C257S735000, C257S666000, C361S813000

Reexamination Certificate

active

06768188

ABSTRACT:

CROSS-REFERENCE TO PRIOR APPLICATION
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-273839, filed on Sep. 19, 2002, the entire content of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, in particular to a package structure for a semiconductor chip.
2. Description of the Related Art
The widespread use of compact electronics devices such as cell phones requires downsizing of semiconductor devices for power control such as power transistors and rectifiers. Lead frames are generally employed as packages for these downsized semiconductor devices. A semiconductor device mounted on a die-pad of the lead frame has an upper electrode, which is connected to an inner lead via a boding wire.
If the upper electrode on the semiconductor device is a source electrode (or drain electrode) that is a current terminal electrode of a transistor, or a cathode electrode (or anode electrode) of a diode, a plurality of bonding wires may often be connected to flow a large capacity of current.
To the contrary, the Applicant has proposed a method of connecting an upper electrode on a device to an inner lead using a plate-like metallic lead (metallic strap) instead of the bonding wire. The lead has lower thermal and electrical resistances than those of the bonding wire (see Japanese Patent Application Laid-Open No. 2002-100716).
A method of ultrasonic die boding or a method of soldering is employed to bond the semiconductor device to the inner lead via the metallic strap. The former is advantageous in production because it can easily rationalize manufacturing facilities. In contrast, the latter is advantageous in wiring resistance and thermal radiation. In particular, the latter is employed frequently in middle- and low-capacity power semiconductor devices.
On the other hand, to meet the needs for downsizing and thinning of a semiconductor device package, it is preferable to lay the metallic strap to the lead in parallel with the semiconductor chip. Such a package structure is exemplified in
FIG. 11. A
semiconductor chip
21
is mounted on a die-pad
22
via a solder
31
. A metallic strap
24
is connected to an upper electrode on the semiconductor chip
21
and to a lead
23
via solders
32
and
33
. This semiconductor device is then molded in a resin
34
.
When the metallic strap
24
is soldered as shown in
FIG. 11
, the solder
32
may project outside the upper electrode at the periphery of the semiconductor chip
21
(in particular, at the terminal thereof at the side of the lead
23
for laying the upper electrode out, as indicated by the arrow shown in FIG.
11
). In such the case, a problem arises on reliability. At the periphery of the semiconductor chip
21
A, dicing lines for chip isolation are located but no insulator film exists. Therefore, if the solder crawls to the periphery, a p-n junction may be short-circuited, for example.
Even though the solder does not extend to the terminal of the chip, a problem also arises if the solder runs on the insulator outside the upper electrode. When a reverse bias is applied to the semiconductor device, a depletion layer is extended to the periphery of the chip. In this case, when a high voltage is applied to a soldered portion above the depletion layer, the depletion layer further reaches the chip's end portion due to the field plate effect. This situation lowers the breakdown voltage of the semiconductor device, for example.
If the metallic strap is flat, it causes a problem on thermal stress because a layer of solder between the metallic strap and the semiconductor chip is thinned. For example, if a large current flows in a high temperature environment, a large thermal stress strain occurs in the semiconductor chip due to a difference in thermal expansion coefficient between the semiconductor chip and the metallic strap and deteriorates the device characteristic. In a word, a sufficient thermal resistance can not be achieved.
The present invention has an object to provide a semiconductor device in a package structure that can improve reliability.
SUMMARY OF THE INVENTION
According to the present invention, a semiconductor device comprises a semiconductor chip having an upper electrode and a lower electrode formed thereon; a package base bonded to the lower electrode on the semiconductor chip; and a metallic strap having first and second ends, said first ends being bonded via a solder to said upper electrode on said semiconductor chip, said second end being bonded to a package lead. The first end of the metallic strap is bonded to the upper electrode in such a manner that a gap therebetween gradually becomes wider in a portion close to said semiconductor chip's edge toward said second end of said metallic strap.


REFERENCES:
patent: 4935803 (1990-06-01), Kalfus et al.
patent: 5001545 (1991-03-01), Kalfus et al.
patent: 5110761 (1992-05-01), Kalfus et al.
patent: 6040626 (2000-03-01), Cheah et al.
patent: 6396127 (2002-05-01), Munoz et al.
patent: 6459147 (2002-10-01), Crowley et al.
patent: 6566164 (2003-05-01), Glenn et al.

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