Semiconductor device

Details Semiconductor device Semiconductor device

2002-07-10

2004-07-13

Hu, Shouxiang (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Integrated circuit structure with electrically isolated...

Including dielectric isolation means

C257S396000, C257S398000, C257S501000, C257S510000

Reexamination Certificate

active

06762477

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device structure and a method of manufacturing the same. In particular, the invention relates to a semiconductor device structure incorporating a plurality of element isolation insulating films having different depths, as well as a method of manufacturing the same.
2. Description of the Background Art
An SOI (Silicon On Insulator) substrate is of a stacked structure in which a silicon substrate (hereinafter also called “semiconductor substrate”), a buried oxide film (hereinafter also called “BOX layer” or “insulating layer”), and a silicon layer (hereinafter also called “semiconductor layer”) are stacked in the order named. Heretofore, the main semiconductor device using an SOI substrate was of the type in which semiconductor elements are surrounded by a full shallow trench isolation (FTI) extending from the upper surface of a semiconductor layer to the upper surface of an insulating layer. The semiconductor device of this type has, as compared to that using a bulk substrate not an SOI substrate, the following advantages: (i) no latch up occurs even with the formation of CMOS transistors; (ii) junction capacitance can be lowered to realize high speed operation; and (iii) the leakage current during standby condition is lessened to reduce power consumption.
However, the semiconductor device of this type has had various problems due to the semiconductor layer being in an electrically floating state, as follows. Firstly, kink effect may occur in I
DS
-V
DS
characteristics, or an operational breakdown voltage may be lowered, because the carrier generated by impact ionization is stored in a lower part of a channel formation region. Secondly, the frequency dependence of a drain conductance (g
0
) may occur because of an unstable potential of the channel formation region. Thirdly, the dependency to switching history may occur in the gate delay time because of an unstable potential of the channel formation region.
To overcome these problems, Japanese Patent Application Laid-Open No. 58-124243 (1983) has proposed a semiconductor device of the type in which a body contact region is selectively formed in an upper surface of a semiconductor layer, and semiconductor elements are surrounded by a partial shallow trench isolation (PTI) extending from the upper surface of the semiconductor layer to such a depth as not to reach the upper surface of an insulating layer. In the semiconductor device of this type, the body contact region and a channel formation region are electrically connected with each other, through the semiconductor layer disposed between the bottom surface of the PTI and the upper surface of the insulating layer. Therefore, the potential of the channel formation region can be fixed by an external power supply connected to the body contact region.
Recently, in order to achieve the scale down of semiconductor devices, there has been proposed a semiconductor device of the type which collectively fixes the potentials of the channel formation regions of a plurality of transistors of the same conductivity type, without individually fixing the potential of a channel formation region per transistor (see Proceedings 1997 IEEE International SOI Conference, Oct. 1997, pp140, 141, 164, 165, 170 and 171). In the semiconductor device of this type, the respective channel formation regions of adjacent transistors are isolated from each other, by a PTI.
Conventional Technique I
One example of the last-mentioned type semiconductor device will be described hereinafter.
FIG. 28
is a top plan view of a semiconductor device structure according to a conventional technique I, and
FIGS. 29 and 30
are sectional views taken along line L
101
and line L
102
, respectively, in the semiconductor device shown in FIG.
28
. For the sake of convenience, interlayer insulating films
127
to
129
shown in
FIGS. 29 and 30
, are omitted in FIG.
28
. Referring to
FIGS. 28
to
30
, the semiconductor device of the conventional technique I comprises a PTI
140
disposed in a PTI formation region
101
; a source/drain region
103
having a high concentration impurity region
118
and low concentration impurity region
119
; a channel formation region
104
(i.e., a P type channel formation region
104
n
and an N type channel formation region
104
p
); source/drain wirings
105
a
and
105
b
; a gate wiring
106
having a stacked structure in which a doped polysilicon layer
121
and metal layer
122
are stacked in the order named; metal wirings
107
and
111
; contact holes
108
,
110
,
125
a
and
125
b
; a body contact region
109
; an SOI substrate
114
having a silicon substrate
115
, BOX layer
116
and silicon layer
117
; a gate oxide film
120
; an insulating film
123
; a sidewall
124
; interlayer insulating films
127
to
129
; a P type channel stopper layer
125
; and an N type channel stopper layer
126
.
Referring to
FIG. 29
, the NMOS and PMOS disposed adjacent each other are isolated by a PTI
140
a
. In the portion of the silicon layer
117
which is sandwiched between the bottom surface of the PTI
140
a
and the upper surface of the BOX layer
116
, the N type channel stopper layer
126
is disposed on the side on which a PMOS formation region is disposed, and the P type channel stopper layer
125
is disposed on the side on which an NMOS formation region is disposed.
Referring to
FIG. 30
, an N
+
type body contact region
109
and an N type channel formation region
104
p
are electrically connected together, through an N type channel stopper layer
126
disposed in the portion of the silicon layer
117
which is sandwiched between the bottom surface of the PTI
140
and the upper surface of a BOX layer
116
. Therefore, the potential of the channel formation region
104
p
can be fixed to the potential of a metal wiring
111
which is electrically connected to the body contact region
109
, via the contact hole
110
filled with a conductive plug.
Conventional Technique II-a
Other conventional semiconductor device structure using a bulk substrate will be described hereinafter.
FIG. 31
is a top plan view of a semiconductor device structure according to a conventional technique II-a, and
FIG. 32
is a sectional view taken along line L
103
in the semiconductor device shown in FIG.
31
. For the sake of simplicity, only the internal structure of a silicon substrate
160
is illustrated in FIG.
32
. Referring to
FIGS. 31 and 32
, the semiconductor device of the conventional technique II-a comprises a silicon substrate
160
; an STI (Shallow Trench Isolation)
163
disposed in an element isolation region
150
; a channel stopper layer
162
; a bottom N well
164
disposed only in a memory cell region of the silicon substrate
160
; a P well
161
overlying the bottom N well
164
and extending across the entire surface of the silicon substrate
160
; a source/drain region
165
; a channel formation region
166
; a plurality of memory cells
151
disposed in the memory cell region of the silicon substrate
160
; a plurality of NMOSs which have a source/drain region
154
and a gate electrode
155
and are disposed in a peripheral circuit region of the silicon substrate
160
on which a sense amplifier, etc. are disposed; a plurality of bit lines
152
; and a plurality of word lines
153
. The bottom N well
164
is provided for improving the soft error tolerance of the memory cells
151
.
Referring to
FIG. 32
, the memory cell region and peripheral circuit region of the silicon substrate
160
are isolated by an STI
163
a
which is formed in such a depth as to extend from the upper surface of the silicon substrate
160
to the upper surface of the channel stopper layer
162
. An STI
163
having the same depth as the STI
163
a
is disposed in the memory cell region and peripheral circuit region of the silicon substrate
160
, respectively.
Conventional Technique II-b
A modification of the semiconductor device according to the conventional technique II-a will be describ

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