Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – Having only two terminals and no control electrode – e.g.,...
Reexamination Certificate
2001-10-17
2004-03-02
Zarabian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
Having only two terminals and no control electrode , e.g.,...
C257S120000
Reexamination Certificate
active
06700141
ABSTRACT:
BACKGROUND OF THE INVENTION
I. Field of the Invention
The present invention relates to a semiconductor structure applicable to semiconductor devices, such as MOSFET's (insulated gate field effect transistors), IGBT's (insulated gate bipolar transistors), bipolar transistors and diodes. Specifically, the present invention relates to a semiconductor structure, that provides a current path in the ON-state of the device and is depleted in the OFF-state of the device to realize a high breakdown voltage and a high current capacity.
II. Description of Related Art
The semiconductor devices may be classified into a lateral device, which has main electrodes thereof arranged on one major surface with a drift current flow parallel to the major surface, and a vertical device, which has the main electrodes thereof distributed on two major surfaces facing opposite to each other and a drift current flow perpendicular to the major surfaces. In the vertical semiconductor device, the drift current flows in the thickness direction of the semiconductor chip (vertically) in the ON-state of the semiconductor device and depletion layers expand also in the thickness direction of the semiconductor chip (vertically) in the OFF-state of the semiconductor device. In the conventional vertical planar-type n-channel MOSFET, the very resistive n-type drift layer thereof provides a drift current path in the ON-state of the MOSFET and is depleted in the OFF-state thereof, resulting in a high breakdown voltage.
Thinning the n-type drift layer, that is shortening the drift current path, facilitates a substantial reduction in the on-resistance, since the drift resistance against the drift current flow is reduced. However, thinning the n-type drift layer narrows the separation width between the drain and the base, limiting the expansion of the depletion layers of the pn-junctions between p-type base regions and the n-type drift layer. Due to the narrow expansion width of the depletion layers, the electric field strength soon reaches the critical value for silicon. Therefore, breakdown is caused at a voltage lower than the designed breakdown voltage of the device. A high breakdown voltage is obtained by increasing the thickness of the n-type drift layer. However, the thick n-type drift layer inevitably causes high on-resistance that further causes loss increase. In other words, there exists a tradeoff relation between the on-resistance and the breakdown voltage.
The tradeoff relation between the on-resistance and the breakdown voltage exists in the other semiconductor devices such as IGBT's, bipolar transistors and diodes. The tradeoff relation also exists in the lateral semiconductor devices, in that the flow direction of the drift current in the ON-state of the device and the expansion direction of the depletion layers by applying a reverse bias voltage in the OFF-state of the device are different from each other. European Patent 0 053 854, U.S. Pat. Nos. 5,216,275, 5,438,215, and Japanese Unexamined Laid Open Patent Application H09-266311 disclose semiconductor devices, which facilitate reducing the tradeoff relation between the on-resistance and the breakdown voltage. The drift layers of the disclosed semiconductor devices are formed of alternating conductivity type layers including heavily doped n-type regions and heavily doped p-type regions. The alternating conductivity type layer, depleted in the OFF-state, facilitates sustaining a high breakdown voltage.
The drift layer of the every disclosed semiconductor device is not a uniform impurity diffusion layer of one conductivity type but an alternating conductivity type layer formed of thin n-type drift regions and thin p-type partition regions laminated alternately. The n-type drift regions and p-type partition regions are shaped with respective thin layers extending vertically. Since the entire drift layer is occupied by the depletion layers expanding laterally from the vertically extending pn-junctions between n-type drift regions and p-type partition regions in the OFF-state of the MOSFET, a high breakdown voltage is obtained even when the impurity concentrations in the n-type drift regions and the p-type partition regions are high.
Japanese Unexamined Laid Open Patent Application No. 2000-40822 discloses the method of manufacturing such a semiconductor device including an alternating conductivity type layer.
FIG. 8
is a cross sectional view of the vertical MOSFET disclosed in U.S. Pat. No. 5,216,275. Referring now to
FIG. 8
, the vertical MOSFET includes a drift layer
12
, that is not a uniform layer but is formed of n-type drift regions
12
a
and p-type partition regions
12
b
arranged alternately. In the figure, p-type well regions
13
, n
+
-type source regions
14
, gate insulation films
15
, gate electrode layers
16
, a source electrode
17
and a drain electrode
18
are shown.
The alternating-conductivity-type drift layer
12
is formed by the epitaxially growing a very resistive n-type layer on an n
++
-type drain layer
11
used for a substrate, by selectively etching trenches in the n-type layer, leaving n-type drift regions
12
a
, and by epitaxially growing p-type partition regions
12
b
in the trenches. Hereinafter, the semiconductor device including an alternating conductivity type layer, that provides a current path in the ON-state of the device and is depleted in the OFF-state of the device, will be referred to as the “super-junction semiconductor device”.
The foregoing publications describe active regions including an alternating conductivity type layer, through which a drift current flows. However, the foregoing publications describe almost nothing on the breakdown withstanding region, usually disposed around the active region to realize a high breakdown voltage. For realizing a practical semiconductor device exhibiting a high breakdown voltage, it is necessary to design the semiconductor structure based on the consideration of the breakdown voltage.
For example, when the thickness of the alternating conductivity type layer in the active region and the thickness thereof in the breakdown withstanding region are the same, a voltage is applied evenly to the n-type drift regions and the p-type partition regions of the alternating conductivity type layer. As a result, depletion layers expand vertically, and the electric field in the active region is relaxed in proportion to the thickness of the alternating conductivity type layer. In the breakdown withstanding region, the surface electric field parallel to the major surface is relaxed by employing a field plate structure or a guard ring structure. However, depletion layers do not expand so widely in the breakdown withstanding region as compared with in the active region. Therefore, the electric field in the breakdown withstanding region is denser than the electric field in the active region. Therefore, the electric field strength in the breakdown withstanding region reaches the critical value sooner than the electric field strength in the active region. As a result, the breakdown withstanding region determines the breakdown voltage of the semiconductor device.
Since the electric field strength in the breakdown withstanding region reaches the critical value sooner than the electric field strength in the active region, an avalanche current is caused in the breakdown withstanding region. The avalanche current, that localizes to the outer p-type region in the active region, makes a parasitic transistor work. Thus, breakdown is caused in the super-junction semiconductor device and the reliability of the super-junction semiconductor device is impaired, Moreover, it is difficult to maintain an avalanche withstanding capability (breakdown withstanding capability) of the super-junction semiconductor device under an inductive load (hereinafter referred to as an “L-load”).
In view of the foregoing, it would be desirable to provide a very reliable super-junction semiconductor device, that facilitates relaxing tradeoff relation between the on-resistance and the breakd
Fujihira Tatsuhiko
Iwamoto Susumu
Onishi Yasuhiko
Sato Takahiro
Ueno Katsunori
Fuji Electric & Co., Ltd.
Rose Kiesha
Rossi & Associates
Zarabian Amir
LandOfFree
Semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3241727