Semiconductor device

Details Semiconductor device Semiconductor device

2002-01-25

2004-05-04

Cao, Phat X. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

With particular power supply distribution means

C257S208000

Reexamination Certificate

active

06730946

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device such as memory or microprocessor.
2. Description of the Related Art
Conventionally, a semiconductor device such as memory and microprocessor comprises a plurality of circuits provided on a semiconductor substrate. Each of the circuits is a combination of a plurality of transistors etc. so as to carry out a certain process. Therefore, the circuits are also called function blocks.
FIG. 11
shows a plane view of an example of a conventional semiconductor device. The semiconductor device comprises a plurality of circuits
102
, each of which has a specific function, mounted on, for example, a rectangular semiconductor substrate
101
. The semiconductor substrate
101
includes an Input/Output region (hereinafter referred to as “IO region”)
103
, which is formed with a predetermined width along the outer region of the substrate
101
, and a chip core region
104
surrounded by the IO region
103
. The circuits
102
are mounted in the chip core region
104
.
FIG. 12
shows an enlarged view of the IO region
103
and its vicinity in the semiconductor device shown in FIG.
11
. The IO region
103
includes signal cells
103
C for transmitting signals between each of the circuits
102
and external devices, as well as first power supply cells
103
A and second power supply cells
103
B for supplying electric power to each of the circuits
102
. The first power supply cells
103
A and the second power supply cells
103
B are connected to external devices (not shown) so as to obtain a first potential (for example, a ground potential) and a second potential, respectively.
In order to distribute the electric power supplied via the first power supply cells
103
A and the second power supply cells
103
B throughout the semiconductor device, the IO region
103
includes a pair of ring wirings arranged around the chip core region
104
, that is, a first trunk
105
and a second trunk
106
. The first trunk
105
and the second trunk
106
are formed on the first power supply cells
103
A, second power supply cells
103
B and signal cells
103
C so as to be at the same level with respect to the semiconductor substrate
101
(that is, on the same surface). The first trunk
105
and the second trunk
106
are not shown in FIG.
11
.
As the first trunk
105
and the second trunk
106
are formed on the same surface, it is difficult to expand their areas, so necessary power supply cannot be obtained. Therefore, the chip core region
104
further includes another pair of ring wirings, that is, a third trunk
107
and a fourth trunk
108
. The third trunk
107
and the fourth trunk
108
are connected to the first power supply cells
103
A and the second power supply cells
103
B, respectively, so as to have the first potential and the second potential, respectively. As shown in
FIG. 11
, the third trunk
107
and the fourth trunk
108
extend so as to be arranged around each of the circuits
102
in the chip core region
104
, and are connected to each of the circuits
102
via branch lines
109
and
110
.
However, such a conventional semiconductor device must have the third trunk
107
and the fourth trunk
108
in the chip core region
104
, so it is difficult to improve the packing density of circuits
102
in the chip core region
104
, which leads to an obstacle to downsizing and higher integration of the semiconductor device.
Further, as the third trunk
107
and the fourth trunk
108
must be arranged in the chip core region
104
, there is a problem that the conventional semiconductor device has a low degree of flexibility in wiring design.
Moreover, as power supply paths from the first power supply cells
103
A and the second power supply cells
103
B to each of the circuits
102
are long, a large voltage drop occurs, which results in a deterioration in circuit characteristics.
SUMMARY OF THE INVENTION
The present invention has been achieved in light of the foregoing problems. It is an object of the invention to provide a semiconductor device capable of reducing its size, increasing its packing density, preventing a deterioration in circuit characteristics, and increasing flexibility in wiring design.
A semiconductor device according to the invention comprises a substrate including a first region and a second region having a ring shape arranged around the first region; a circuit provided in the first region of the substrate and having a predetermined function; and a power supply wiring provided in the second region of the substrate to supply electric power to the circuit, and having a laminated structure with a first power supply layer corresponding to a first potential, and a second power supply layer corresponding to a second potential.
In the semiconductor device according to the invention, as the power supply wiring of a laminated structure includes the first power supply layer and the second power supply layer, compared with a case where the first and second power supply layers are arranged on the same surface, each area of the first and second power supply layers can be expanded, so a enough supply capability of electric power can be obtained without providing additional trunks.


REFERENCES:
patent: 5148263 (1992-09-01), Hamai
patent: 5949098 (1999-09-01), Mori
patent: 6324677 (2001-11-01), Fischer et al.

Affiliated with

Also associated with

Rating

Semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3229283