Semiconductor device

Details Semiconductor device Semiconductor device

2002-02-28

2004-04-27

Nhu, David (Department: 2818)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

On insulating substrate or layer

C438S289000, C438S197000

Reexamination Certificate

active

06727152

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor device, and, more particularly, to a technique which is effective for application to a semiconductor device having a field effect transistor formed in a semiconductor layer provided on an insulating layer.
DESCRIPTION OF THE RELATED ART
An attempt has been made to use a semiconductor base having a so-called SOI (Silicon On Insulator) structure provided with an insulating layer composed of silicon oxide between a semiconductor substrate composed of monocrystal silicon and a thin semiconductor layer composed of monocrystal silicon and to form a field effect transistor in a semiconductor layer of the semiconductor base in a semiconductor device, such as a field effect transistor. The field effect transistor has a channel forming region (body region), a gate insulator, a gate electrode and a pair of semiconductor regions corresponding to source and drain regions and has a structure wherein the bottoms of the pair of semiconductor regions corresponding to the source and drain regions are brought into an insulating layer of a semiconductor base. Since the field effect transistor can reduce pn junction capacities (parasitic capacities) added to the source and drain regions by portions equivalent to contact areas of the respective bottoms of the pair of semiconductor regions, a fast switching speed can be achieved.
On the other hand, since the periphery of the channel forming region is surrounded by a pair of semiconductor regions and the insulating layer of the semiconductor base, the above-described field effect transistor has a reduced threshold voltage (Vth) as compared with the case in which a field effect transistor is formed in a semiconductor base comprised of a normal bulk substrate. Therefore, a method of providing a feeding contact region (body electrode) electrically connected to a channel forming region within a semiconductor layer of a semiconductor base and applying a potential to the feeding contact region to thereby vary the threshold voltage has been proposed for a partial depletion type field effect transistor, in which a channel forming region is not completely depleted, but some remains as a neutral region. This method has been disclosed in, for example, 1997 IEEE International Solid-State Circuit Conference, Digest of Technical Papers, 6869 TP 4.3 [A 1V 46 ns 16 Mb SOI-DRAM with Body Control Technique].
Further, a method of providing a back gate electrode below an insulating layer of a semiconductor base, as opposed to a channel forming region, and applying a potential to the back gate electrode to thereby change the threshold voltage has been proposed for a complete depletion type field effect transistor wherein the channel forming region is completely depleted. This method has been disclosed in Japanese Patent Application Laid-open No. Hei 7-131025.
However, the present inventors have found the following problems as a result of discussions about the aforementioned technique.
(1) When the partial depletion type field effect transistor is of, for example, an n channel conduction type, a p type channel forming region produces a depleted region due to a gate electric field and potentials applied to its source and drain, and some of this region serves as a neutral region. When a VGS potential is applied to a gate-electrode, a VS potential (=0[V]) is applied to one semiconductor region, a VDS potential (≧VS potential) is applied to the other semiconductor region, and a VSub potential (≦0[V]) is applied to a feeding contact region, a channel current flows so that electrons and holes are developed in a high field region near the drain. The electrons flow into a drain region which is higher in potential, whereas the holes flow into a neutral region which is low in potential. The holes are drawn or drained to the feeding contact region through the neutral region. Since, however, the resistance of the neutral region is high, the neutral region becomes high in potential. Since the electrons flow from the source to a channel according to a bipolar operation when the neutral region is high in potential, the occurrence of the holes increases in the high field region near the drain. A problem arises in that, since the potential of the neutral region increases more and more due to the circulation of these series of mechanisms, the withstand voltage for the drain becomes low. A further problem arises in that the threshold voltage becomes unstable. These problems arise similarly even in the case of a p channel conduction type.
(2) When the complete depletion type field effect transistor is of, for example, an n channel conduction type, each channel forming region is completely depleted. Therefore, there is no escape route for holes produced in a high field region near its drain. Therefore, a problem arises in that, since all of the generated holes flow into a source region, the withstand voltage for the drain becomes low due to a bipolar operation. A further problem arises in that, since the channel forming region is completely depleted, the threshold voltage cannot be increased. A method of changing the threshold of a complete depletion type field effect transistor by a back gate bias has been disclosed in Japanese Patent Application Laid-open No. Hei 1(1989)-115394. Since, however, the potential of a lower portion (lower surface portion) of a channel forming region is lowered by a minus back gate potential, as indicated by its detailed discussions, holes generated in the vicinity of the drain are stored in a lower portion of a channel forming region and hence the threshold voltage becomes unstable. These problems arise similarly even in the case of a p channel conduction type.
(3) The partial depletion type field effect transistor and the complete depletion type field effect transistor are respectively low in threshold voltage and also low in drain withstand voltage as described above. Thus, since the threshold voltage cannot be changed in a stable state, a standby current becomes large and hence a standby current test cannot be carried out. Further, since the withstand voltage for the drain is low, high-voltage aging cannot be performed.
An object of the present invention is to provide a technique which is capable of increasing the withstand voltage for a drain of a field effect transistor formed in a semiconductor layer provided on an insulating layer.
Another object of the present invention is to provide a technique which is capable of achieving a stabilization of a threshold voltage of a field effect transistor formed in a semiconductor layer provided on an insulating layer.
A further object of the present invention is to provide a technique which is capable of changing a threshold voltage of a field effect transistor formed in a semiconductor layer provided on an insulating layer in a stable state.
The above, other objects and novel features of the present invention will become apparent from the description of the present SPECIFICATION and the accompanying drawings.
SUMMARY OF THE INVENTION
Summaries of typical aspects of the present invention as disclosed in the present application will be described in brief as follows:
A semiconductor device having a field effect transistor formed in a semiconductor layer provided on a insulating layer comprises a body electrode electrically connected to a channel forming region of the field effect transistor, and a back gate electrode provided below the insulating layer and opposed to the channel forming region of the field effect transistor.
In the case of a partial depletion type field effect transistor, a potential for inducing an electrical charge of conduction type opposite to a channel formed in an upper portion of the channel forming region of the field effect transistor, in a lower portion of the semiconductor layer opposite to the back gate electrode, is applied to each of the body electrode and the back gate electrode.
In the case of a complete depletion type field effect transistor, a potential (negative potenti

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