Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage
Reexamination Certificate
2002-08-05
2004-04-06
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific identifiable device, circuit, or system
With specific source of supply or bias voltage
C327S538000, C327S333000, C365S226000
Reexamination Certificate
active
06717460
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor devices, and particularly to a structure of an internal voltage generation circuit generating an internal voltage of the semiconductor device from an external power supply voltage. More particularly, the present invention relates to a control structure for a deep power down mode that prohibits an internal voltage generation operation.
2. Description of the Background Art
FIG. 21
schematically shows a structure of an array of a conventional dynamic random access memory (DRAM). In
FIG. 21
, a memory cell MC is arranged corresponding to a crossing of bit lines BL and ZBL and a word line WL. In
FIG. 21
, memory cell MC arranged corresponding to a crossing of bit line BL and word line WL is depicted as a representative thereof. Memory cells MC are arranged in rows and columns. Word line WL is arranged corresponding to each memory cell row. A pair of bit lines BL and ZBL is arranged corresponding to each memory cell column. Memory cell MC is arranged corresponding to a crossing of one bit line of the bit lines and a word line.
For bit lines BL and ZBL, there are provided a bit line equalize circuit BPE for precharging and equalizing bit lines BL and ZBL to the level of a bit line precharge voltage Vb
1
, and a sense amplifier SA for amplifying the difference of the voltages of bit lines BL and ZBL and latching the amplified voltage. For sense amplifier SA, there are provided a sense activation transistor ASPT rendered conductive when a sense amplifier activation signal/SAP is active, to couple a sense power supply line transmitting an array power supply voltage Vdds of a high level power supply node to sense amplifier SA, and a sense amplifier activation transistor ASNT render conductive when a sense amplifier activation signal SAN is active, to couple to a sense ground line transmitting a ground voltage Vss to a low level power supply node of sense amplifier SA.
Memory cell MC includes a memory capacitor MC storing information in the form of charges, and an access transistor MT for coupling memory cell capacitor MC with a corresponding bit line (or ZBL) according to a signal voltage on word line WL. Access transistor MT is generally formed of an N channel MOS transistor (insulated gate field effect transistor). A negative bias voltage Vbb is applied to the back gate of access transistor MT. By applying the negative bias voltage Vbb to the back gate of access transistor MT, the threshold voltage is rendered stable, the parasitic capacitance between the signal line and the substrate region is reduced, and the junction capacitance of drain/source of the access transistor is reduced.
A bit line equalize circuit BPE transmits a bit line precharge voltage Vbl of an intermediate voltage (Vdds/2) of an array power supply voltage Vdds to bit lines BL and ZBL according to a bit line equalize designating signal BLEQ.
Word line WL is driven to the level of a high voltage Vpp higher than array power supply voltage Vdds when selected. By driving a selected word line WL to the level of high voltage Vpp, data of an H level corresponding to array power supply voltage Vdds can be stored in the node of memory capacitor MC without any loss due to the threshold voltage of access transistor MT of memory cell MC.
Memory capacitor MQ receives a constant cell plate voltage Vcp at an electrode node (cell plate node) facing to the storage node that stores data. In general, this cell plate voltage Vcp corresponds to the voltage level of the intermediate voltage (Vdds/2) of array power supply voltage Vdds.
Thus, a plurality of kinds of voltages at different voltage levels are employed in a DRAM as described above. In the case where the plurality of kinds of voltages are generated externally and then applied to the DRAM, the system scale will be increased. Also, power consumption of the entire system will increase (due to wiring loss). Furthermore, the number of power supply terminals will increase in the DRAM. Therefore, the plurality of kinds of voltages are generated inside the DRAM.
FIG. 22
schematically shows a structure of the portion related to internal voltages of the DRAM. Referring to
FIG. 22
, the DRAM includes a memory cell array
902
having a plurality of memory cells (memory cell MC of
FIG. 21
) arranged in rows and columns, a control circuit
904
responsive to an externally applied command CMD for generating an operation control signal required to perform an operation mode specified by command CMD, a row select circuit
906
rendered active under control of control circuit
904
to drive to a selected state a word line arranged corresponding to an addressed row in memory cell array
902
according an externally applied row address signal RA, a sense amplifier group
908
selectively rendered active by control circuit
904
to sense, amplify and latch data of memory cells on the row selected by row select circuit
906
, a column select circuit
910
operating under control of control circuit
904
to select a memory cell in an addressed column in memory cell array
902
according to an externally applied column address signal CA when active, and an internal voltage generation circuit
900
generating various internal voltages Vpp, Vbb, Vbl, Vcp, Vdds and Vddp from an external power supply voltage EXVDD.
A periphery power supply voltage Vddp from internal voltage generation circuit
900
is applied to control circuit
904
and row select circuit
906
. A high voltage Vpp from internal voltage generation circuit
900
is applied to row select circuit
906
. In row select circuit
906
, there are provided a row decoder receiving the peripheral power supply voltage Vddp as an operation power supply voltage and a word line driver receiving a high voltage Vpp. A row select signal is generated by the row decode circuit through decoding of a received row address signal. The word line driver transmits a word line select signal of the level of high voltage Vpp to a word line arranged corresponding to a row selected by the row select signal generated by the row decode circuit.
Memory cell array
902
is supplied with bit line precharge voltage Vbl, cell plate voltage Vcp and a negative bias voltage Vbb applied to the substrate region of memory cell array
902
. Array power supply voltage Vdds is applied to sense amplifier group
908
as an operating power supply voltage of the sense amplifiers. In general, periphery power supply voltage Vddp is applied to column select circuit
910
as an operating power supply voltage (column select signal may be at the level of array power supply voltage Vdds).
By operating the peripheral circuit such as control circuit
904
with periphery power supply voltage Vddp and operating sense amplifier group
908
related to memory cell array
902
with array power supply voltage Vdds, the peripheral circuit is operated at high speed to achieve high speed access, while the breakdown voltage of the access transistor and memory cell capacitor of memory cell MC is ensured to allow data to be stored stably.
FIG. 23
schematically shows a structure of internal voltage generation circuit
900
of FIG.
22
. Referring to
FIG. 23
, internal voltage generation circuit
900
includes a constant current source
950
generating a constant current of a constant level from external power supply voltage EXVDD, reference voltage generation circuits
951
,
952
and
953
converting the constant current from constant current source
950
into a voltage to generate a reference voltage Vrefd for high voltage, a reference voltage Vrefp for periphery power supply voltage and reference voltage Vrefs for array power supply voltage, respectively, a negative voltage generation circuit
954
receiving external power supply voltage EXVDD as an operating power supply voltage to generate a negative voltage Vbb, and a high voltage generation circuit
955
receiving external power supply voltage EXVDD as an operating power supply voltage to generate a high voltage Vpp.
Negative voltage gener
Matsumoto Junko
Okamoto Takeo
Tian Zengcheng
Yamauchi Tadaaki
Cunningham Terry D.
Renesas Technology Corp.
Tra Quan
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